Internal Voltage Trimming Circuit With Offset Cancellation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor data storage apparatuses face challenges in generating stable internal voltages due to external noise and process parameter changes, which can lead to malfunctions during voltage trimming operations, especially when using external test equipment.
Innovation Solution
An internal voltage trimming circuit is implemented within the semiconductor apparatus, comprising an integral circuit for sampling and integrating voltage differences, an offset cancellation unit to mitigate noise and parameter changes, a comparison circuit for adjusting trimming codes, and a code average signal generation circuit to generate a final trimming code, ensuring stable voltage generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external test equipment is used for voltage trimming, then trimming accuracy can be achieved, but test time and cost increase
Solution Approach 1:
The patent implements a built-in self-test (BIST) apparatus that enables the semiconductor apparatus to perform voltage trimming autonomously without external test equipment. The BIST apparatus includes an integral circuit, comparison circuit, and code generation circuit that work together to automatically trim the internal voltage to the target level, thereby reducing test time and cost while maintaining trimming accuracy.
Solution Approach 2:
The patent introduces a BIST apparatus as an intermediary component within the semiconductor apparatus that mediates the voltage trimming process. This intermediary enables autonomous trimming by generating test signals, comparing voltages, and adjusting trimming codes without requiring external test equipment, thus resolving the contradiction between trimming accuracy and test time.
2Measurement precision
If external test equipment is used for voltage trimming, then voltage can be trimmed to target level, but test cost increases
Solution Approach 1:
The BIST apparatus enables the semiconductor apparatus to perform voltage trimming autonomously, eliminating the need for expensive external test equipment. By integrating the trimming functionality within the device itself, the patent reduces test cost while maintaining the ability to trim voltage to the target level accurately.
3Device complexity
If internal voltage is generated without offset cancellation, then circuit complexity is reduced, but voltage stability deteriorates due to external noise and process parameter changes
Solution Approach 1:
The patent implements a feedback mechanism through the comparison circuit that continuously monitors the internal voltage and compares it with a reference voltage. The comparison result is fed back to the code generation circuit, which adjusts the trimming code to maintain voltage stability despite external noise and process parameter changes. This feedback loop ensures voltage reliability while managing circuit complexity.
Solution Approach 2:
The patent applies offset cancellation through the integral circuit before voltage comparison to prevent the influence of external noise and process parameter changes on the trimming process. By performing preliminary offset cancellation, the system ensures accurate voltage comparison and stable internal voltage generation without requiring overly complex circuitry.
4Speed
If trimming code is adjusted rapidly, then voltage response speed improves, but accuracy deteriorates due to noise and parameter changes
Solution Approach 1:
The patent performs offset cancellation through the integral circuit before the comparison circuit adjusts the trimming code. This preliminary action removes the influence of external noise and process parameter changes from the voltage signal, enabling accurate trimming code adjustment even when voltage response speed is increased. The offset-cancelled signal provides a clean basis for precise voltage trimming.
Data Source
AI summary
A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage.