Voltage Variable Material ESD Protection Substrate
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Solution Overview
Problem
Conventional ESD protection methods struggle to provide adequate protection for integrated circuits with higher ESD threat voltage capability and lower parasitic loading effect within limited package sizes, especially for ICs with increased I/O pins, while maintaining compactness and performance.
Innovation Solution
The proposed ESD protection structure incorporates a substrate with a voltage variable material (VVM) layer and a via connecting two surfaces, where the VVM is in a conductive state during ESD events to form a discharge path to a ground terminal, and in an isolation state otherwise, allowing for efficient energy dissipation without additional package size or complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection methods are used, then ESD protection can be provided, but the package size increases and parasitic loading effect increases
Solution Approach 1:
The patent combines the ESD protection function with the existing substrate structure by integrating voltage variable material directly into the substrate layers. The VVM is incorporated between signal layers and ground planes, merging protection functionality with the carrier structure itself, thereby avoiding additional package size while providing effective ESD protection.
Solution Approach 2:
The patent utilizes the vertical dimension of the substrate by placing voltage variable material between different layers (signal layer and ground plane). This three-dimensional integration allows ESD protection without increasing the horizontal package footprint, effectively using the substrate thickness dimension to accommodate protection elements.
2Reliability
If conventional ESD protection methods are used, then ESD protection can be provided, but parasitic loading effect (capacitance) increases
Solution Approach 1:
The patent employs voltage variable material whose electrical parameters (conductivity, permittivity) change dynamically based on applied voltage. During normal operation, the VVM maintains low permittivity to minimize parasitic capacitance. During ESD events, it transitions to high conductivity state to provide protection, thereby reducing parasitic loading while maintaining protection capability.
Solution Approach 2:
The voltage variable material provides dynamic response to ESD events by transitioning between different electrical states. The material remains in high impedance state during normal operation to minimize parasitic effects, and switches to low impedance state only when ESD voltage exceeds the threshold, thereby reducing continuous parasitic loading while providing on-demand protection.
3Productivity
If IC package size is reduced to accommodate more chips, then more chips can be implemented, but ESD protection becomes more difficult to provide
Solution Approach 1:
The patent moves ESD protection elements from the horizontal plane to the vertical dimension by integrating voltage variable material between substrate layers. This allows ESD protection functionality to be embedded within the substrate thickness rather than consuming horizontal space, enabling compact package design with high chip density while maintaining protection capability.
Solution Approach 2:
The patent merges ESD protection functionality with the substrate structure itself by incorporating voltage variable material as an integral part of the substrate layers. This integration eliminates the need for separate protection components that would consume package space, allowing increased chip density while providing comprehensive ESD protection across all I/O pins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively enhances ESD protection efficiency by enabling the transmission of large ESD currents to ground, reducing damage risk while maintaining mechanical integrity and compactness, and can be tailored for various ESD parameters through controlled conductor thickness and spacing.
Implementation Method 1
a voltage variable material (VVM) layer and a via connecting two surfaces, where the VVM is in a conductive state during ESD events to form a discharge path to a ground terminal, and in an isolation state otherwise
Implementation Method 2
a via connecting the first and second surfaces; and a first metal layer disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path
Data Source
AI summary
An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.