VOQ Network Switch Multi-Stage Arbitration Fabric Scheduler

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional network switches face challenges in achieving high performance efficiency due to long packet-in-and-out latency in store-and-forwarding approaches and the complexity of interface channelization, while cut-through switching requires continuous forwarding at a constant speed, leading to potential packet errors.

Innovation Solution

A VOQ-based network switch architecture that supports interface channelization and cut-through switching, featuring a multi-stage arbitration fabric scheduler that generates schedule requests to avoid underrun and ensures continuous data transmission across the switch fabric, reducing latency and preventing packet errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If store-and-forwarding approach is used, then packet buffering capacity is improved, but packet-in-and-out latency increases significantly

Engineering Contradiction:
Improvepacket buffering capacityVSAvoidpacket-in-and-out latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the switching process into two independent phases: packet reception at ingress ports and packet forwarding at egress ports. The ingress logic receives packets and stores them in VOQs, while the egress logic independently manages packet forwarding. This segmentation allows packets to be forwarded as soon as they are received and scheduled, eliminating the need to wait for complete packet reception at both ends, thus reducing latency while maintaining buffering capacity through VOQs.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by having the ingress logic fully receive and store packets in VOQs before the egress logic begins forwarding them. The fabric scheduler pre-allocates bandwidth and schedules packet transmission in advance, ensuring that packets are ready for immediate forwarding without causing underrun conditions. This preliminary preparation enables cut-through switching to proceed smoothly with reduced latency.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If cut-through switching is used, then system latency is reduced, but packet errors occur due to non-constant forwarding speed

Engineering Contradiction:
Improvesystem latencyVSAvoidpacket transmission accuracy
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent implements feedback mechanisms through the fabric scheduler that continuously monitors the state of packets in the switch fabric and adjusts scheduling decisions accordingly. The scheduler receives feedback about packet positions, transmission progress, and bandwidth utilization, and uses this information to dynamically adjust forwarding rates. This feedback loop ensures that packets are forwarded at the required constant speed to prevent errors while still achieving low latency through efficient scheduling.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent employs dynamic scheduling where the fabric scheduler adaptively adjusts packet forwarding rates based on real-time conditions. The scheduler can vary the speed of packet transmission through the fabric depending on traffic patterns, packet priorities, and fabric utilization, ensuring that critical packets receive constant speed treatment to prevent errors while allowing flexibility for other traffic. This dynamic approach maintains reliability while optimizing latency.

Inventive Principle:
Principle #15Dynamics

3Productivity

If interface channelization is implemented, then network switch throughput is enhanced, but design complexity increases

Engineering Contradiction:
Improvenetwork switch throughputVSAvoidnetwork switch design complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a universal VOQ-based architecture that can handle multiple interface channelization configurations through a single unified fabric scheduler. The same switching fabric and scheduling mechanism support various port groupings and channel configurations without requiring separate specialized hardware for each configuration. This multi-functionality achieves enhanced throughput through interface channelization while minimizing design complexity by using a universal approach.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent enables interface channelization by dynamically changing the parameters of port grouping and aggregation. The fabric scheduler can reconfigure which physical ports are grouped together logically, allowing flexible creation of channelized interfaces with different bandwidths and configurations. This parameter-based approach allows the system to adapt to different throughput requirements without changing the fundamental hardware architecture, thus enhancing productivity while controlling complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11483259B2VOQ-based network switch architecture using multi-stage arbitration fabric scheduler
Publication Date: 2022.10.25 MARVELL ASIA PTE LTD
  • US11483259B2 patent drawing
  • US11483259B2 patent drawing
  • US11483259B2 patent drawing

AI summary

A network switch is capable of supporting cut-through switching and interface channelization with enhanced system performance. The network switch includes a plurality of ingress tiles, each tile including a virtual output queue (VOQ) scheduler operable to submit schedule requests to a fabric scheduler. Data is requested in unit of quantum, which may aggregate multiple packets, and which reduces schedule latency. Each request is associated with a start-of-quantum (SoR) state or a middle-of-quantum (MoR) state to support cut-through. The fabric scheduler performs a multi-stage scheduling process to progressively narrow the selection of requests, including stages of arbitration in virtual output port level, virtual output port group level, tile level, egress port level, and port group level. Each tile receives the grants for its requests and accordingly sends request data to a switch fabric for transmission to the destination egress ports.