Voting Circuit Synchronization for Parallel Finite State Machines

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Solution Overview

Problem

In systems with multiple finite state machines, existing methods fail to ensure synchronization and prevent catastrophic failures due to loss of synchronization when voting is not available, leading to system malfunctions.

Innovation Solution

A method using a precharge-conditional discharge circuit for voting, where selected finite state machines generate a ready signal to proceed, and if none are selected, at least one non-selected machine's ready signal is waited for, ensuring a unanimous vote before proceeding, thereby maintaining system synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple asynchronous finite state machines are operated in parallel, then productivity is improved, but synchronization reliability deteriorates

Engineering Contradiction:
Improveparallel operation capabilityVSAvoidsynchronization reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a voting mechanism as an intermediary between multiple finite state machines to achieve synchronization. The voting circuit aggregates ready signals from all machines and generates a unified proceed signal only when all machines are ready, thereby mediating the synchronization between asynchronous operations and preventing synchronization loss while maintaining parallel operation capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements feedback through ready signals that continuously report the operational status of each finite state machine back to the voting mechanism. This feedback loop enables the system to dynamically adjust and wait for all machines to be ready before proceeding, ensuring synchronization reliability while allowing parallel execution

Inventive Principle:
Principle #23Feedback

2Reliability

If a voting mechanism is implemented to ensure synchronization, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the voting mechanism with the existing ready signal infrastructure of the finite state machines. The voting circuit combines multiple ready signals into a single proceed signal using logical AND operations, integrating the synchronization function into the existing control flow without requiring separate complex synchronization circuits for each machine pair

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The voting mechanism serves multiple functions simultaneously: it acts as a synchronization point, a status aggregation device, and a control signal generator. This multi-functionality reduces the need for additional dedicated circuits for each function, thereby limiting the increase in device complexity while achieving reliable synchronization

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8384420B2Preventing hangs in a system with synchronized operation using stalls
Publication Date: 2013.02.26 TEXAS INSTRUMENTS INC
  • US8384420B2 patent drawing
  • US8384420B2 patent drawing
  • US8384420B2 patent drawing

AI summary

This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention selects a set of the finite state machines to participate in an operation. If one or more of the finite state machines are selected for operation, the method waits until all selected finite state machines generate the ready signal. If none of the finite state machines are selected for operation, the method waits until at least one non-selected finite state machine generates the ready signal. This waiting can be accomplished with a precharge-conditional discharge circuit used for voting.