3D NAND Memory Vpass Step Reduces Hot Carrier Injection
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Solution Overview
Problem
Program disturb occurs in memory devices due to high control gate-to-channel voltage across unselected memory cells during programming, leading to inadvertent programming of unselected memory cells, especially when there is a significant change in channel voltage between selected and unselected word lines in a 3D NAND string structure.
Innovation Solution
The program pulse on a selected word line is applied in two steps: an initial increase to an intermediate level and then to a peak level, with the voltage on the adjacent unselected word line temporarily increased above its nominal level during the second step to reduce the channel gradient and prevent program disturb. This approach includes adjusting the elevated pass level based on the program loop number, program-erase cycles, and temperature to enhance the countermeasure effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high program voltage is applied to the selected word line to program memory cells efficiently, then programming speed is improved, but program disturb occurs in unselected memory cells due to high control gate-to-channel voltage
Solution Approach 1:
The patent applies preliminary action by temporarily increasing the voltage on the unselected word line WLn-1 to an elevated pass level Vpass_el before and during the application of the program pulse to WLn. This preemptive voltage adjustment prevents the formation of a large channel voltage gradient that would otherwise cause hot carrier injection and program disturb in unselected memory cells, while still allowing the program operation to proceed at high speed.
Solution Approach 2:
The patent changes the voltage parameter of the unselected word line WLn-1 from the nominal pass level Vpass to an elevated pass level Vpass_el during the program operation. This parameter adjustment reduces the channel gradient between selected and unselected word lines, thereby suppressing hot carrier injection into the charge trapping material of unselected memory cells while maintaining programming efficiency on the selected word line.
2Object-affected harmful factors
If the voltage on unselected word lines is increased to prevent program disturb, then program disturb is reduced, but the complexity of voltage control increases
Solution Approach 1:
The patent segments the voltage control into distinct phases: a first step increasing voltage from an initial level to the nominal pass level Vpass, and a second step increasing voltage to the elevated pass level Vpass_el during the program pulse application. This segmented approach simplifies the control logic by breaking down the complex voltage adjustment into manageable sequential steps, making it easier to implement in memory controllers.
3Object-affected harmful factors
If a two-step voltage increase is applied to the selected word line with elevated pass level on unselected word line, then program disturb is reduced, but the programming operation time increases
Solution Approach 1:
The patent employs periodic action by applying the elevated pass level Vpass_el on the unselected word line WLn-1 only during the specific time window when the program pulse is applied to WLn. The elevated voltage is not maintained continuously but periodically activated during the program operation, thereby minimizing the additional time required while still effectively preventing program disturb during the critical programming phase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces program disturb by minimizing the channel gradient between word lines, thereby preventing unintended programming of unselected memory cells, especially during high program voltage operations, and is adaptable to varying conditions such as temperature and cycle counts.
Implementation Method 1
This patent addresses program disturb caused by hot carrier injection type mechanisms in 3D NAND memory devices
Data Source
AI summary
Apparatuses and techniques are described for reducing an injection type of program disturb in a memory device. A voltage on a selected word line is increased in a first step from an initial level such as 0 V to an intermediate, pass level such as Vpass, and in a second step from Vpass to a peak program level of Vpgm. A voltage on an adjacent unselected word line can be increased from the initial level to Vpass and then temporarily increased to an elevated level of Vpass_el during the second step increase on the selected word line. This helps reduce the magnitude of a channel gradient between the selected word line and the adjacent word line. The increase to Vpass_el may be implemented for program loops in the later part of a program operation, when Vpgm and the risk of program disturb is relatively high.