VPX Connector Soldered Interface for 25 Gbps Signal Integrity
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Solution Overview
Problem
Conventional VPX connectors face challenges in supporting 25 Gbps data rates with Bit Error Rates (BER) of 1E-15 or better due to crosstalk issues in the via field, limiting their performance in high-speed communication applications, especially in avionics and military environments.
Innovation Solution
The solution involves a novel refinement to VPX connector pins and a Printed Wiring Board (PWB) structure using Double Transition (DT) vias, which reduce cross talk by minimizing parasitic capacitance, combined with a soldered interface created by applying solder using a jet paste dispenser and stencil screen printer, and a reflow process to form a solder joint between the circuit board and connector pin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional VPX connectors are used, then connector compatibility and ease of manufacture are maintained, but crosstalk increases and data rate performance deteriorates at 25 Gbps
Solution Approach 1:
The patent applies different via structures (DT vias, blind vias, buried vias) to different locations within the connector interface. Specifically, DT vias are used at the connector interface to minimize parasitic capacitance and crosstalk, while other via structures are used in less critical areas. This localized optimization of via structures resolves the contradiction by improving signal integrity at the critical interface without requiring complete redesign of the entire board structure.
Solution Approach 2:
The via structure is segmented into multiple types (DT vias, blind vias, buried vias) with different functions and characteristics. DT vias are specifically designed for the connector interface to handle high-speed signals, while other via types serve different purposes in the board structure. This segmentation allows each via type to be optimized for its specific function, resolving the crosstalk issue at the connector interface while maintaining overall manufacturability.
2Reliability
If DT vias are implemented to reduce crosstalk, then signal integrity improves, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The DT vias and other complex via structures are pre-designed and pre-positioned during the PCB fabrication process. The via locations, dimensions, and structures are determined in advance based on signal integrity requirements, allowing the complex structures to be integrated into the standard PCB manufacturing workflow. This preliminary planning reduces the perceived complexity by converting it into a design-phase consideration rather than a manufacturing-phase challenge.
3Object-generated harmful factors
If blind vias are used instead of through-vias, then crosstalk is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses plated through-holes and conductive traces as intermediary elements to connect the blind vias to the rest of the circuit. The blind vias are precisely positioned and plated, then connected to surface pads through controlled impedance traces. This intermediary approach allows the blind via structure to achieve its crosstalk reduction benefit while the standard plated through-hole technology handles the precision alignment requirements, distributing the manufacturing complexity across multiple standard processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed data communication at 25 Gbps with low BER (<1E-15) while surviving harsh environmental conditions, such as those found in avionics, by minimizing cross talk and ensuring reliable connectivity.
Implementation Method 1
using a jet paste dispenser to apply first solder into a plated contact cavity
Implementation Method 2
using a stencil screen printer to apply second solder (a) over the plated contact cavity
Implementation Method 3
performing a reflow process to heat the first and second solder so as to create a solder joint
Implementation Method 4
a first trace disposed on an exposed surface of the core substrate that is in electrical contact with the first via
Data Source
AI summary
Systems and methods for providing a soldered interface between a circuit board and a connector pin. The methods comprise: using a jet paste dispenser to apply first solder into a plated contact cavity formed in the circuit board; using a stencil screen printer to apply second solder (a) over the plated contact cavity which was at least partially filled with the first solder by the jet paste dispenser and (b) over at least a portion of a pad surrounding the plated contact cavity; inserting the connector pin in the plated contact cavity such that the connector pin passes through the second solder and extends at least partially through the first solder; and performing a reflow process to heat the first and second solder so as to create a solder joint between the circuit board and the connector pin.