VRD Peak-Efficiency Power Capping for Processor Loads

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Solution Overview

Problem

The efficiency of Voltage Regulator Devices (VRDs) diminishes beyond their peak efficiency point due to varying loads, necessitating a method to maintain optimal operation.

Innovation Solution

A Baseboard Management Controller (BMC) generates an efficiency histogram for the VRD, identifies the power output level at peak efficiency, and sets a power cap for the processor to prevent operation beyond this level, thereby maintaining VRD efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the processor operates at high power output levels, then processing performance is improved, but VRD efficiency deteriorates due to operating beyond peak efficiency point

Engineering Contradiction:
Improveprocessing performanceVSAvoidVRD efficiency
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The system dynamically adjusts the power cap for the processor based on real-time monitoring of VRD efficiency metrics. The BMC continuously monitors VRD input and output power, calculates efficiency, and adjusts the power cap accordingly to maintain operation at or near peak efficiency points, resolving the contradiction between maintaining high performance and avoiding efficiency deterioration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements a feedback loop where the BMC monitors VRD efficiency metrics, identifies when the VRD operates beyond its peak efficiency point, and responds by adjusting the power cap to prevent further efficiency degradation. This closed-loop control ensures the processor operates within efficiency-optimal boundaries while maintaining maximum acceptable performance.

Inventive Principle:
Principle #23Feedback

2Power

If the processor operates beyond VRD peak efficiency point, then processing capability is improved, but power draw increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower draw
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

The power cap is dynamically adjusted based on monitored VRD efficiency metrics rather than being fixed. The BMC continuously adapts the power cap to maintain operation at peak efficiency points, ensuring optimal power utilization while preserving processing capability within efficiency boundaries.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the power cap parameter based on VRD efficiency characteristics. By monitoring efficiency metrics and adjusting the power cap parameter accordingly, the system optimizes the balance between processing capability and power draw, preventing operation in inefficient high-power regions.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the processor operates beyond VRD peak efficiency point, then processing performance is improved, but heat generation increases

Engineering Contradiction:
Improveprocessing performanceVSAvoidheat generation
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The feedback mechanism monitors VRD efficiency and prevents operation in regions that generate excessive heat. By adjusting the power cap based on efficiency metrics, the system avoids the high-heat generation zones that occur when the VRD operates beyond its peak efficiency point, thereby controlling temperature while maintaining acceptable performance.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12632104B2Operating a voltage regulator at peak efficiency
Publication Date: 2026.05.19 LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE LTD
  • US12632104B2 patent drawing
  • US12632104B2 patent drawing
  • US12632104B2 patent drawing

AI summary

Methods, systems, and products for operating a VRD at peak efficiency includes: generating, during operation of a computing system that includes a VRD providing power to a processor, an efficiency histogram for the VRD, identifying, from the efficiency histogram, a power output level associated with the VRD operating at peak power efficiency, and setting a power cap for the processor at the power output level.