Vread Bias Allocation on Word Lines for 3D Memory Read Disturb
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Solution Overview
Problem
In 3D non-volatile memory devices, the non-uniform memory hole diameter leads to varying programming and erase speeds, causing read disturb issues that reduce the reliability of memory cells, especially in the erased state, due to the strong electric field affecting unselected memory cells during sensing operations.
Innovation Solution
Adjusting read pass voltages (Vrp) based on memory hole diameters, setting higher Vrp for wider portions and lower Vrp for narrower portions to equalize read disturb across word line layers, and determining programming speeds to optimize programming and sensing operations by using trim values for initial programming voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a uniform read pass voltage is applied to all word line layers, then the sensing operation is simplified, but read disturb varies significantly across different word line layers due to non-uniform memory hole diameters
Solution Approach 1:
The patent applies different read pass voltages to different word line layers based on their local characteristics (memory hole diameter). Word line layers adjacent to narrower memory hole portions receive lower read pass voltages, while those adjacent to wider portions receive higher voltages, optimizing read disturb reduction for each local region
Solution Approach 2:
The patent changes the read pass voltage parameter across different word line layers to compensate for manufacturing variations. By adjusting the voltage level according to the memory hole diameter at each layer, the system maintains reliable sensing operation while minimizing read disturb effects
2Measurement precision
If higher read pass voltage is used to ensure proper sensing, then sensing accuracy is maintained, but read disturb increases for memory cells in narrower memory hole portions
Solution Approach 1:
The patent tailors the read pass voltage to the local memory hole diameter at each word line layer. Narrower portions receive lower voltages to prevent excessive read disturb, while wider portions receive higher voltages to ensure adequate sensing signal, thus maintaining sensing accuracy without uniformly increasing read disturb
Solution Approach 2:
The patent uses measured programming speeds as feedback to determine the appropriate read pass voltage for each word line layer. Since programming speed correlates with memory hole diameter, this feedback mechanism enables dynamic voltage adjustment that balances sensing accuracy and read disturb reduction
3Reliability
If manufacturing precision of memory hole diameter is improved, then read disturb is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of improving manufacturing precision, the patent changes the operational parameter (read pass voltage) to compensate for manufacturing variations. This approach achieves read disturb reduction through software/firmware control rather than hardware/manufacturing improvements, avoiding increased manufacturing complexity
Solution Approach 2:
The patent enables the memory device to self-characterize its own memory hole diameters through programming speed measurements and automatically adjust read pass voltages accordingly. This self-service approach eliminates the need for external precision manufacturing or complex testing equipment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces worst-case read disturb, maintains sensing accuracy, and ensures consistent channel resistance, thereby improving the reliability and performance of 3D non-volatile memory devices without modifying the reference current used during sensing.
Implementation Method 1
the strong electric field affecting unselected memory cells during sensing operations
Data Source
AI summary
Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations in a memory hole diameter. The memory cells are in NAND strings which extend in the memory holes. A larger read pass voltage is used for memory cells which are adjacent to wider portions of the memory holes, and a smaller read pass voltage is used for memory cells which are adjacent to narrower portions of the memory holes. This approach reduces the worst-case read disturb. Further, an overall resistance in the NAND string channel may be substantially unchanged so that a reference current used during sensing may be unchanged. The read pass voltage may be set based on a program voltage trim value, which is indicative of programming speed and memory hole diameter.