Pseudo-Differential Input Receiver With Vref-Adjustable Helper FETs
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Solution Overview
Problem
Conventional CMOS input receivers face performance degradation and increased power consumption when operating at higher frequencies due to the need for multiple parallel configurations to support a wide range of Vref values, leading to inefficiencies in area and power usage.
Innovation Solution
A Vref adjustable self-biased pseudo-differential input receiver is implemented, which includes helper FETs to monitor and adjust the Vref line, allowing a single receiver configuration to operate over a wide frequency and Vref range with minimal impact on die area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple parallel input receivers are configured to support wide-range frequency and Vref values, then the receiver can cover a broader operating range, but the die area and power consumption increase significantly
Solution Approach 1:
The patent implements a single input receiver that can universally handle multiple Vref values (from 0.5Vdd to 0.7Vdd) and frequency ranges (200MHz to 533MHz) through dynamic configuration. The receiver uses a multiplexer to select between different termination resistors and adjusts its operating parameters based on the detected Vref value, eliminating the need for multiple dedicated receivers for different Vref ranges while maintaining full adaptability across the specified operating conditions
2Adaptability or versatility
If multiple parallel input receivers are configured to support wide-range frequency and Vref values, then the receiver can cover a broader operating range, but the power consumption increases due to multiple active circuits
Solution Approach 1:
The patent employs dynamic configuration within a single receiver circuit, using a multiplexer to switch between different termination resistors (Rterm1, Rterm2) and adjusting the receiver's operating state based on the detected Vref value and frequency range. This dynamic adaptation allows the receiver to maintain optimal performance across 200MHz to 533MHz frequencies and various Vref levels while keeping only one receiver circuit active at any given time, thereby minimizing power consumption compared to having multiple parallel receivers operating simultaneously
3Adaptability or versatility
If multiple parallel receivers are implemented, then support for different Vref values is achieved, but performance degrades due to increased input capacitance and input-path delay
Solution Approach 1:
The patent applies local quality optimization by providing different termination resistor values (Rterm1 for Vref=0.5Vdd, Rterm2 for Vref=0.7Vdd) matched to specific Vref conditions. The multiplexer selects the appropriate termination resistor based on the detected Vref value, ensuring that each local operating condition has an optimized termination match. This approach maintains input signal integrity and minimizes reflections for each specific Vref level without requiring multiple parallel receivers, thereby avoiding the cumulative input capacitance and delay issues
Data Source
AI summary
A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5˜0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance.


