VRR Display Scan Timing for Flicker Prevention

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Solution Overview

Problem

Display devices experience flicker phenomena due to variations in operating frequency and Display Bright Value (DBV), which existing technologies fail to adequately address.

Innovation Solution

Adjusting the scan timing for applying stress voltage to pixels based on operating frequency and luminance band to prevent flicker, by varying the pulse width and toggle timing of the third scan signal in variable refresh rate (VRR) mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the operating frequency is varied in VRR mode to adapt to different image types, then the power consumption and responsiveness are optimized, but the flicker characteristics deteriorate and cause visible flicker phenomena

Engineering Contradiction:
Improverefresh rate adaptabilityVSAvoidflicker phenomenon
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies dynamics by making the scan timing adjustable based on operating frequency. The gate driver circuit dynamically modifies the timing of scan signals (particularly the third scan signal for stress voltage application) according to the current refresh rate, allowing the system to adapt to different VRR modes while maintaining stable pixel operation and preventing flicker across varying frequencies

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the timing parameters of scan signals based on operating frequency. Specifically, the pulse width and toggle timing of the third scan signal are adjusted according to the refresh rate, transforming the fixed timing approach into a variable parameter system that compensates for frequency changes and eliminates flicker characteristics

Inventive Principle:
Principle #35Parameter changes

2Illumination intensity

If the DBV (Display Bright Value) is adjusted according to user settings to control brightness, then the display comfort is improved, but the flicker characteristics vary and cause flicker phenomena

Engineering Contradiction:
Improvedisplay brightnessVSAvoidflicker phenomenon
Core Design Contradiction:
Illumination intensityVSObject-affected harmful factors

Solution Approach 1:

The patent adjusts timing parameters of scan signals in response to DBV changes. When brightness settings change, the system modifies the timing of stress voltage application (third scan signal) to compensate for the interaction between brightness level and flicker perception, ensuring stable display across different brightness conditions

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If the scan timing for applying stress voltage is fixed to simplify the control circuit, then the device complexity is reduced, but the flicker prevention capability deteriorates when operating frequency varies

Engineering Contradiction:
Improvecontrol circuit complexityVSAvoidflicker phenomenon
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The gate driver circuit incorporates dynamic timing adjustment capability where the scan signal timing (especially the third scan signal) is modified based on operating frequency feedback. This dynamic approach prevents flicker while maintaining reasonable circuit complexity by using existing circuit elements with adjustable timing characteristics

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12361877B2Display device operating in variable refresh rate based on operating frequency and driving method
Publication Date: 2025.07.15 LG DISPLAY CO LTD
  • US12361877B2 patent drawing
  • US12361877B2 patent drawing
  • US12361877B2 patent drawing

AI summary

Disclosed are a display device in which a scan timing for applying a stress voltage to a pixel is adjusted based on an operating frequency to prevent a flicker phenomenon even when the operating frequency varies, and a method for operating the same. The display device includes a display panel including a plurality of pixel circuits; and a gate driver circuit configured to provide an emission signal, a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to each of the plurality of pixel circuits, wherein when the display device operates in a variable refresh rate (VRR) mode, the display device is configured to adjust a time at and/or a time duration for which the third scan signal is enabled based on an operating frequency in each of a refresh frame and an anode reset frame, wherein the third scan signal is defined as a signal for applying an on-bias stress voltage to a pixel circuit.