VRR Panel Frame Duration Balancing to Prevent Flicker
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Solution Overview
Problem
Existing display technologies experience flicker and DC imbalance due to tight timing requirements in synchronous protocols like DisplayPort, leading to issues with variable refresh rates and power consumption, especially in Panel Self Refresh (PSR) scenarios.
Innovation Solution
Implement techniques on the graphics source or sink side to adjust refresh rates based on detected PLL drift, skipping or repeating frames, and extending blanking periods to maintain synchronization within the display panel's supported range, using DisplayPort auxiliary channels for communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synchronous protocols (DisplayPort/eDP) are used to deliver pixel data, then timing precision and synchronization are improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the synchronization function from the pixel data stream by using a separate auxiliary channel (DDC/I2C) to convey timing information. This separates the high-precision timing requirements from the main data path, reducing the complexity of the synchronous protocol while maintaining timing precision.
Solution Approach 2:
The patent introduces an intermediary mechanism (frame counter and timing information packets) that mediates between the host device and display controller. This intermediary translates asynchronous frame delivery into synchronized display updates, achieving precise timing control without requiring complex synchronous protocols for all data transmission.
2Use of energy by moving object
If variable refresh rates are implemented, then power consumption is reduced, but flicker and DC imbalance occur
Solution Approach 1:
The patent implements a feedback mechanism where the display controller monitors the actual refresh rate and frame timing, then communicates timing corrections back to the host device via the auxiliary channel. This feedback loop allows the system to dynamically adjust frame delivery timing to maintain stable panel operation and eliminate flicker, even when using variable refresh rates for power savings.
Solution Approach 2:
The patent makes the refresh rate dynamic by allowing the display controller to independently adjust the timing of frame updates based on panel state and content requirements. The system can transition between different refresh rates (e.g., 30Hz, 60Hz, 120Hz) and even insert blanking periods dynamically, optimizing power consumption while maintaining visual stability through adaptive timing control.
3Object-affected harmful factors
If frame timing is adjusted to maintain synchronization, then flicker is eliminated, but frame duration variability increases
Solution Approach 1:
The patent uses preliminary action by having the host device send timing information packets in advance with each frame, containing predicted timing requirements. The display controller uses this advance information to prepare for upcoming frame updates, adjusting blanking periods and refresh timing proactively to prevent flicker before it occurs, rather than reacting to timing errors after they arise.
Data Source
AI summary
In one embodiment, a display system includes circuitry to, after an exit from a self-refresh state, obtain first frame data with a first refresh rate and second frame data with a second refresh rate different than the first refresh rate, and based on the second refresh rate being greater than the first refresh rate, determine an amount of drift between timing controller circuitry of a graphics controller and timing controller circuitry of a display panel, and based on the amount of drift being above a threshold value, cause the first frame data to not be displayed and cause the second frame data to be displayed at the first refresh rate.