VSB Lithography Mask Patterns with ILT–MWCO Co-Optimization
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Solution Overview
Problem
Existing reticle enhancement technologies (RET) for semiconductor lithography, particularly using variable shaped beam (VSB) lithography, face challenges in efficiently producing precise and resilient mask patterns due to high computational demands, complex OPC features, and manufacturing variations, leading to increased costs and reduced yield.
Innovation Solution
The implementation of Mask Wafer Co-optimization (MWCO) methods that combine inverse lithography technology (ILT) with model-based Mask Data Preparation (MDP) to optimize mask patterns for manufacturability and wafer quality, reducing computational time and improving the process window without additional fracturing or Manhattanization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional RET methods with OPC features are used, then mask patterns can be produced, but computational time and complexity increase significantly
Solution Approach 1:
The patent inverts the conventional approach by using inverse lithography technology (ILT) to directly calculate the optimal mask pattern that will produce the desired wafer pattern, rather than starting with the design pattern and applying corrective OPC features. This inversion fundamentally changes the optimization direction and reduces computational complexity.
Solution Approach 2:
The patent changes the optimization parameters from adjusting individual OPC feature geometries to optimizing the entire mask pattern simultaneously using ILT algorithms. This parameter transformation allows the system to achieve the same manufacturing precision with reduced computational time by working in a different optimization space.
2Reliability
If conventional RET methods are used, then mask patterns can be produced, but the process window is limited
Solution Approach 1:
The patent applies preliminary optimization actions by using ILT to pre-calculate the optimal mask pattern that inherently accounts for process variations. This preliminary action embeds robustness against manufacturing variations directly into the mask design, expanding the process window before actual fabrication begins.
Solution Approach 2:
The patent incorporates feedback mechanisms through iterative optimization loops that simulate the lithography process and adjust the mask pattern to maximize the process window. The system continuously refines the mask design based on simulated process variations, ensuring optimal wafer quality across different manufacturing conditions.
3Manufacturing precision
If additional fracturing or Manhattanization is applied, then mask patterns can be optimized, but device complexity and costs increase
Solution Approach 1:
The patent extracts and eliminates the need for additional fracturing and Manhattanization steps by directly generating manufacturing-ready mask patterns through ILT. This extraction removes unnecessary intermediate processing steps, reducing both device complexity and associated costs while maintaining mask manufacturability.
Data Source
AI summary
Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a substrate design, wherein a low-pass filter is applied to the substrate design to form a target wafer pattern. An initial mask pattern is determined from the target wafer pattern. An initial set of VSB shots is determined based on the initial mask pattern. A substrate pattern is calculated from a simulated mask pattern calculated with the initial set of VSB shots. The target wafer pattern is compared with the substrate pattern, and the initial set of VSB shots is adjusted until the substrate pattern and the target wafer pattern are within a predetermined tolerance. The adjusting of the initial set of VSB shots creates an adjusted set of VSB shots.