Virtually Substrate-less Power Semiconductor Device Handling
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Solution Overview
Problem
Existing methods for manufacturing ultra-thin power semiconductor chips face challenges in handling fragility and require non-standard equipment, as the thinning process complicates wafer handling and increases substrate resistance, especially for vertical power devices.
Innovation Solution
A virtually substrate-less composite power semiconductor device (VSLCPSD) is developed, featuring a sandwich structure with a power semiconductor device, a front-face device carrier, and an intervening bonding layer, which provides structural rigidity and low substrate resistance through patterned metallization and conductive vias, allowing for thinning without compromising mechanical support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the substrate thickness is reduced to make thin chips, then bulk device electrical resistance and thermal resistance are reduced, but the wafer becomes more fragile and difficult to handle
Solution Approach 1:
A support structure comprising a first support layer and a second support layer is introduced as an intermediary element. The first support layer is formed on the backside of the semiconductor wafer, and the second support layer is formed on the front side, providing mechanical support during processing. This mediator allows the wafer to be thinned to ultra-thin dimensions while maintaining handleability and structural integrity throughout fabrication.
2Length of stationary object
If the substrate is thinned to under 50 microns, then low profile and reduced substrate thickness are achieved, but the wafer becomes extremely fragile requiring non-standard equipment
Solution Approach 1:
The support layers are formed on the wafer before the thinning process is completed. The first support layer is deposited on the backside, and the second support layer is formed on the front side, creating a mechanically robust structure that enables standard dicing and handling equipment to process ultra-thin wafers without requiring specialized ultra-precision equipment.
3Ease of operation
If the substrate is made thicker to provide mechanical support, then wafer stability and ease of handling are improved, but device electrical resistance and thermal resistance increase
Solution Approach 1:
The support function is segmented from the active device region. The support layers are formed as separate structural elements on the front and back sides of the wafer, allowing the bulk substrate to be thinned for low resistance while the support layers provide the necessary mechanical stability. This segmentation enables independent optimization of electrical performance and mechanical handling.
4Ease of manufacture
If conventional dicing and grinding processes are used, then standard manufacturing procedures are maintained, but post-thinning wafer processing becomes difficult or impossible
Solution Approach 1:
The support layers are formed in advance before final thinning and dicing operations. This preliminary structuring allows conventional dicing blades and grinding equipment to process the wafer through standard procedures, while the pre-formed support layers remain intact to enable subsequent post-thinning processing steps such as bonding and assembly that would otherwise be impossible on ultra-thin substrates.
Data Source
AI summary
A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD. The diminishing thickness TPSD effects a low back substrate resistance and the through-carrier conductive vias effect a low front-face contact resistance to the front-face device metallization pads.