VSoC Linear Array Processor for Barcode Detection
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Solution Overview
Problem
Current symbology reading systems face challenges in detecting and decoding one-dimensional barcodes, especially when the scanner is in motion or at an angle, and when codes have low contrast, leading to inadequate capture and decoding events due to limitations in image capture and processing rates.
Innovation Solution
A system and method utilizing a Vision System on a Chip (VSoC) with a linear array processor (LAP) and single instruction multiple data (SIMD) architecture, which processes pixel data in rows simultaneously, allowing for efficient ROI finding, tracking, and feature extraction, reducing the need for a trigger and enhancing decoding capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional image capture and processing systems are used, then the system structure is simple, but the image capture and processing rate is insufficient to detect barcodes during motion or at angles
Solution Approach 1:
The patent segments the image processing task into distinct stages: a first image sensor captures images at a higher rate for trigger generation, while a second image sensor processes images at a lower rate for final decoding. This segmentation allows the system to achieve high effective processing rates without requiring the entire system to operate at maximum speed, thus balancing performance with complexity.
Solution Approach 2:
The patent combines multiple image sensors with different capture rates into a single integrated system. The first image sensor operates at a higher frame rate to detect motion and generate triggers, while the second sensor captures images at a lower rate for actual decoding. By merging these sensors and coordinating their operations through shared processing logic, the system achieves high-speed barcode detection without proportionally increasing overall system complexity.
2Area of stationary object
If the scanner operates in motion or at an angle, then the coverage area increases, but the number of successful decoding events decreases due to inadequate capture rates
Solution Approach 1:
The system performs preliminary action by using the first image sensor to capture images and generate triggers before the actual decoding process. This preliminary capture at higher rates ensures that barcodes in motion or at angles are detected and triggers are generated in advance, allowing the second sensor to capture the appropriate frames for successful decoding, thus maintaining reliability across larger coverage areas.
3Ease of operation
If a trigger-based system is used, then the processing logic is simple, but it requires precise triggering which is difficult to achieve with moving scanners
Solution Approach 1:
The system implements self-service by enabling the first image sensor to automatically generate triggers based on its own captured images. The trigger generation is performed autonomously by the system itself through image analysis, eliminating the need for external triggering mechanisms or precise manual triggering, thus improving ease of operation while distributing processing responsibilities.
4Productivity
If conventional processing rates are used, then energy consumption is lower, but the number of capture events per second is insufficient for rapid motion scanning
Solution Approach 1:
The patent applies partial action by having the first image sensor operate at a higher frame rate specifically for trigger generation, while the second sensor operates at a lower rate for actual decoding. This partial high-rate operation provides sufficient capture events for rapid motion scanning without requiring the entire system to consume energy at maximum rate, thus achieving improved productivity with moderate energy consumption.
Data Source
AI summary
This invention provides a system and method for capturing, detecting and extracting features of an ID, such as a 1D barcode, that employs an efficient processing system based upon a CPU-controlled vision system on a chip (VSoC) architecture, which illustratively provides a linear array processor (LAP) constructed with a single instruction multiple data (SIMD) architecture in which each pixel of the rows of the pixel array are directed to individual processors in a similarly wide array. The pixel data are processed in a front end (FE) process that performs rough finding and tracking of regions of interest (ROIs) that potentially contain ID-like features. The ROI-finding process occurs in two parts so as to optimize the efficiency of the LAP in neighborhood operations—a row-processing step that occurs during image pixel readout from the pixel array and an image-processing step that occurs typically after readout occurs. The relative motion of the ID-containing ROI with respect to the pixel array is tracked and predicted. An optional back end (BE) process employs the predicted ROI to perform feature-extraction after image capture. The feature extraction derives candidate ID features that are verified by a verification step that confirms the ID, creates a refined ROI, angle of orientation and feature set. These are transmitted to a decoding processor or other device.