VT Invariant SDRAM Write Leveling via Digital Phase Shifting
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Solution Overview
Problem
Current memory designs for DDR3 and DDR4 SDRAM face challenges in maintaining proper signal timing due to voltage and temperature variations, leading to timing skew issues and requiring repeated write-leveling procedures, which degrades system performance.
Innovation Solution
A method and apparatus for synchronizing clock, write strobe, and write data signals using phase shifts that are voltage and temperature invariant, eliminating the need for physical delay lines and allowing for fast rank switching by applying calculated phase shifts during startup, reducing jitter and duty cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If physical delay lines are used for write-leveling, then timing skew is compensated, but jitter and duty cycle distortion increase
Solution Approach 1:
The patent replaces physical delay lines with a digital phase-shifting mechanism. Instead of using analog delay elements that introduce jitter and distortion, the invention uses a counter to generate phase-shifted clock signals that control digital signal timing. This substitution of mechanical/analog components with digital logic eliminates the harmful effects while achieving the same timing alignment function.
Solution Approach 2:
The patent changes the parameter of time delay to phase shift. Rather than using fixed physical delay lines that create absolute time delays, the invention uses variable phase shifts controlled by a counter. This allows the timing adjustment to be made relative to the clock signal phase, providing flexibility without the drawbacks of physical delay elements.
2Manufacturing precision
If write-leveling procedure is repeated periodically, then timing accuracy is maintained, but system performance degrades
Solution Approach 1:
The patent performs the timing calibration action once during system initialization rather than repeatedly during operation. The counter is configured to generate the correct phase shifts from the start, eliminating the need for periodic write-leveling procedures that would interrupt normal system operation and degrade performance.
Solution Approach 2:
The phase-shifting mechanism is designed to automatically maintain timing accuracy without requiring external intervention or repeated calibration procedures. Once the counter is initialized with the correct phase shift values, the system self-corrects for timing variations without degrading performance.
3Ease of manufacture
If fixed 45-degree phase shifts are used, then implementation is simplified, but timing is not calibrated for VT variations
Solution Approach 1:
The patent transitions from fixed phase shifts to dynamic, adjustable phase shifts. Instead of using hard-coded 45-degree shifts, the invention uses a counter that can be configured to generate variable phase shifts based on actual timing requirements. This allows the system to adapt to voltage and temperature variations while maintaining implementation simplicity through digital control.
4Manufacturing precision
If large physical delay lines are used, then timing skew is corrected, but signal integrity is degraded
Solution Approach 1:
The patent replaces large physical delay lines with a digital phase-shifting approach. This substitution eliminates the signal integrity problems caused by long analog delay paths while maintaining the ability to correct timing skew through digital control of phase relationships.
Data Source
AI summary
A method, non-transitory computer readable medium and apparatus for synchronizing a clock signal data path, a write strobe signal data path and a write data signal data path are disclosed. The method determines an amount of phase shift between the clock signal data path and the write strobe signal data path and between the clock signal data path and the write data signal data path, gates a clock signal to generate strobe clock signals that are phase shifted by at least one phase shift, applies a fine phase shift to the strobe clock signals where the strobe clock signals have an overall phase shift that is approximately equal to the amount of phase shift, and synchronizes a launch of the clock signal data path, the write strobe signal data path, and the write data signal data path using the strobe clock signals with the overall phase shift.