Vt-Modifiable Transistor Memory Cell for Compact Storage
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Solution Overview
Problem
SRAM cells are large and consume significant power, and alternatives like NOR, 1T1R, and 1T1C memory cells have slower access speeds and larger area requirements, necessitating a more efficient memory cell design for reduced area and power consumption.
Innovation Solution
A memory cell comprising a Vt-modifiable n-channel transistor and a Vt-modifiable p-channel transistor connected in parallel with a differential sense amplifier, allowing for faster access speeds and reduced area usage by sensing current differences, which enables compact information storage and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM cells are used, then access speed is high, but area consumption is large and power consumption is high
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage-based storage (SRAM) to threshold voltage modifiable transistor storage. By using Vt-modifiable transistors where information is stored as a change in threshold voltage rather than voltage state, the cell achieves SRAM-like speed with significantly reduced area (2 transistors vs 6 transistors).
Solution Approach 2:
The patent extracts the essential storage function from the traditional 6-transistor SRAM structure, retaining only the critical components (2 Vt-modifiable transistors) needed for storage while eliminating redundant circuitry. The differential sense amplifier externally provided allows the core storage element to be minimized.
2Speed
If SRAM cells are used, then access speed is high, but power consumption is high
Solution Approach 1:
By changing from voltage-based to threshold voltage-based storage, the patent eliminates the continuous refresh operation required by DRAM and the static leakage current inherent in SRAM. The Vt-modifiable transistor maintains its state without continuous power, achieving low static power consumption while maintaining fast access when needed.
Solution Approach 2:
The patent transitions from continuous periodic refresh (DRAM) or continuous static bias (SRAM) to periodic programming only when data needs to be stored or updated. Once programmed, the threshold voltage change maintains state without periodic intervention, reducing overall power consumption while preserving fast access capability.
3Area of stationary object
If alternative memory cells (NOR, 1T1R, 1T1C) are used, then area consumption is reduced, but access speed becomes much smaller
Solution Approach 1:
The patent adopts threshold voltage modifiable transistors as the storage mechanism, which enables fast switching and access similar to SRAM. The Vt-modifiable transistor can rapidly switch between states and respond quickly to read operations, overcoming the speed limitation of conventional alternative memory cells while maintaining small area.
Solution Approach 2:
The patent introduces Vt-modifiable transistors as an intermediary between SRAM and other alternative memory cells. This intermediate approach combines the fast access of SRAM with the compact structure of alternative cells, achieving a balance that neither extreme can provide alone.
4Area of stationary object
If fewer transistors are used, then area consumption is reduced, but maintaining complementary signals becomes difficult
Solution Approach 1:
The patent uses asymmetric transistor types (n-channel and p-channel) with complementary characteristics. The n-channel transistor responds to positive voltage changes while the p-channel responds to negative voltage changes, creating naturally complementary signals from a single stored bit. This asymmetry in transistor characteristics enables reliable complementary output from a minimal 2-transistor structure.
Data Source
AI summary
The present disclosure relates to a memory cell, a memory array, and methods for writing a memory cell. In an example embodiment, a memory cell comprises a first transistor, a second transistor, and a differential sense amplifier. The first transistor is a Vt-modifiable n-channel transistor and the second transistor is a Vt-modifiable p-channel transistor, each transistor having first and second main electrodes. The first main electrodes of the first and second transistors are connected together. The differential sense amplifier is connected to the second main electrodes of the first and the second transistor. The differential sense amplifier is adapted for sensing the current difference between the first transistor and the second transistor.