Differential Voltage-to-Time Converter With Common-Mode Tracking

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Solution Overview

Problem

Existing voltage-to-time converters (VTCs) face limitations in noise and linearity, which affect the resolution of time-domain circuits such as data converters and frequency synthesizers, often requiring trade-offs that compromise gain.

Innovation Solution

A high linearity voltage ramp is implemented in VTCs to reduce noise sensitivity, and the performance is made independent of common mode input voltage by using a shared ramp signal and adjustable inverter thresholds to track environmental changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If linearity is optimized in VTC circuits, then measurement precision is improved, but VTC gain is reduced

Engineering Contradiction:
ImprovelinearityVSAvoidVTC gain
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The VTC circuit is divided into multiple independent inverter stages, each contributing to the overall voltage-to-time conversion. This segmentation allows optimization of linearity in individual stages while maintaining sufficient gain through the cumulative effect of multiple stages, resolving the contradiction between linearity and gain.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A shared ramp signal is introduced as an intermediary element that is common to all inverter stages. This shared ramp provides a stable reference that improves linearity of the conversion process without requiring individual stage optimization that would compromise gain. The ramp signal mediates between the linearity requirements and gain requirements of the system.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If VTC circuits are designed for high gain, then productivity is improved, but noise sensitivity increases

Engineering Contradiction:
ImproveVTC gainVSAvoidnoise sensitivity
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

Multiple inverter stages are merged into a unified VTC architecture with shared ramp signal and common timing reference. This merging provides noise immunity through differential operation and common-mode rejection, allowing high gain to be achieved without proportionally increasing noise sensitivity. The combined structure averages out random noise while maintaining the cumulative gain effect.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If inverter thresholds are made fixed, then device complexity is reduced, but adaptability to environmental changes deteriorates

Engineering Contradiction:
Improveinverter threshold controlVSAvoidenvironmental tracking
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The inverter thresholds are made dynamically adjustable through control circuits that modify the threshold voltages based on detected minimum signal levels. This dynamic adaptation allows the VTC to track environmental changes such as temperature variations and process shifts, maintaining optimal performance without requiring overly complex fixed-threshold design compensations.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12355465B2Low noise inverter-based voltage-to-time converter with common mode input tracking
Publication Date: 2025.07.08 INTEL CORP
  • US12355465B2 patent drawing
  • US12355465B2 patent drawing
  • US12355465B2 patent drawing

AI summary

A differential voltage-to-time converter (VTC) architecture and method of providing VTC signals are disclosed. The VTC includes a ramp generator that generates a ramp voltage, capacitors having a bottom plate coupled with the ramp generator to receive the ramp voltage, and inverters having inputs coupled to top plates of the capacitors to provide signals based on a sampled signal. A threshold voltage or supply voltage of the inverters tracks a minimum input signal voltage.