Voltage-to-Time Converter Linearization for Low-Voltage PAM Signaling
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high data bandwidths due to limitations in multi-level signaling schemes, particularly at low supply voltages, which affect the performance of voltage-based receivers and increase power consumption.
Innovation Solution
A time-based receiver system that includes a voltage-to-time converter (VTC) with linearization circuits, which generates output signals with different delay times to identify data values and compensates for inter-symbol interference, allowing for efficient data reconstruction at low supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage-based receivers are used to achieve high data bandwidths, then communication speed is improved, but power consumption increases and performance degrades at low supply voltages
Solution Approach 1:
The patent replaces voltage-based signal processing with time-based signal processing. The voltage-to-time converter transforms input voltage levels into proportional time delays, and the time-based receiver processes signals in the time domain rather than voltage domain. This substitution enables high data bandwidth achievement while operating at low supply voltages with reduced power consumption, as time-based processing is inherently more energy-efficient than voltage-based processing at high speeds.
2Productivity
If multi-level signaling schemes are implemented to increase data bandwidth, then communication speed is improved, but signal integrity deteriorates due to inter-symbol interference
Solution Approach 1:
The patent introduces linearization circuits as intermediary components between the voltage-to-time converter and the rest of the receiver system. These linearization circuits specifically compensate for inter-symbol interference (ISI) by correcting the distorted time delay signals. The intermediary linearization stage enables multi-level signaling to maintain signal integrity despite the presence of ISI, allowing high data bandwidth transmission through schemes like PAM4 while preserving reliable signal detection.
3Device complexity
If voltage-to-time conversion is performed without linearization, then device complexity is reduced, but measurement precision deteriorates due to non-linear delay characteristics
Solution Approach 1:
The patent segments the voltage-to-time conversion process into multiple stages: the initial voltage-to-time conversion stage, followed by separate linearization circuits for each output path. This segmentation allows the system to maintain relatively simple individual circuit blocks while achieving high overall measurement precision. Each linearization circuit is a discrete, manageable module that corrects non-linearities in its specific signal path, enabling accurate delay time measurement without requiring a completely complex monolithic design.
Data Source
AI summary
A voltage-to-time converter (VTC) includes: a first inverter electrically connected between a first node, to which a clock signal is applied, and a second node, a first buffer electrically connected to the second node and to output a first output signal, a second inverter electrically connected between a third node, to which the clock signal is applied, and a fourth node, a second buffer electrically connected to the fourth node to output a second output signal, a first linearization circuit configured to receive a first input signal and electrically connected between the first node and the second node, and a second linearization circuit configured to receive a second input signal and electrically connected between the third node and the fourth node.