Vertical Transport CMOS Transistors Asymmetric Threshold Voltage
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Solution Overview
Problem
Current semiconductor technologies face challenges in miniaturization and performance enhancement, particularly in achieving asymmetric threshold voltage in vertical transport field effect transistors (VTFETs) due to limitations in channel doping and electric field distribution, which affect carrier mobility and device scalability beyond the 7 nanometer technology node.
Innovation Solution
The implementation of a dual channel epitaxy configuration in VTFETs, utilizing Low-Ge-Content (LGC) SiGe near the source and High-Ge-Content (HGC) SiGe as the main channel, creates an asymmetric threshold voltage profile that enhances the electric field and carrier mobility by steepening the potential distribution near the source side, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional channel doping methods are used in VTFETs, then device fabrication is simplified, but asymmetric threshold voltage cannot be achieved
Solution Approach 1:
The patent applies local quality by creating different Ge content regions within the channel epitaxy layer. The channel epitaxy layer has a first region with first Ge content and a second region with second Ge content, where the Ge contents differ. This local compositional variation enables asymmetric threshold voltage without requiring complex external doping processes, directly resolving the contradiction between manufacturing simplicity and threshold voltage asymmetry.
Solution Approach 2:
The patent changes the Ge content parameter within the channel epitaxy layer to achieve asymmetric threshold voltage. By varying the Ge content from the first region to the second region during epitaxial growth, the patent creates the desired asymmetry in threshold voltage while maintaining a relatively simple fabrication process, as the composition gradient is introduced during the growth phase rather than requiring subsequent complex doping steps.
2Productivity
If device miniaturization is pursued beyond 7nm node, then integration density increases, but performance enhancement becomes difficult
Solution Approach 1:
The patent uses composite material structure by combining regions with different Ge content (first Ge content and second Ge content) within the same channel epitaxy layer. This composite approach allows the device to maintain high integration density through miniaturization while achieving performance enhancement through the asymmetric Ge distribution, which creates favorable electric field effects and carrier mobility improvements in the scaled device.
Data Source
AI summary
A semiconductor structure for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including the SiGe layer and a second material layer formed on the SiGe layer, a first high-κ metal gate disposed over the first set of fins, and a second high-κ metal gate disposed over the second set of fins. An asymmetric threshold voltage is present along the channel of the VTFET in a region defined at a bottom of the first and second set of fins, and a Ge content of the second material layer is higher than a Ge content of the SiGe layer.