Voltage-to-Delay Converter Circuit With Kick Signal for Linearity
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Solution Overview
Problem
Existing voltage to delay (VTD) converters in analog to digital converters (ADCs) face challenges in achieving high signal-to-noise ratio (SNR), bandwidth, and linearity due to trade-offs between these metrics, with current starved inverter and ramp and comparator architectures leading to nonlinear responses and noise, while duplicated architecture solutions still suffer from linearity issues and prolonged reset periods.
Innovation Solution
A new VTD circuit architecture with multiple instances of a duplicated architecture, incorporating a kick signal to improve linearity and reduce effective capacitor requirements, allowing for simultaneous enhancement of SNR, bandwidth, and power consumption, with a design that overlaps voltage to delay and reset periods to increase conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current starved inverter architecture is used, then bandwidth is improved, but linearity and signal-to-noise ratio deteriorate
Solution Approach 1:
The VTD converter is divided into multiple independent parallel paths (first and second paths with different delay amounts). This segmentation allows each path to operate with simpler, faster circuitry while maintaining overall linearity through the combination of paths, resolving the contradiction between bandwidth and linearity.
Solution Approach 2:
A delay amount determination circuit acts as an intermediary that calculates optimal delay values for each path based on input voltage. This mediator ensures that the combined output maintains linearity while allowing individual paths to operate at high speeds, resolving the bandwidth-linearity tradeoff.
2Measurement precision
If ramp and comparator architecture is used, then signal-to-noise ratio is improved, but linearity and bandwidth deteriorate
Solution Approach 1:
The conversion process is segmented into multiple parallel paths with different delay characteristics. This allows the system to achieve high signal-to-noise ratio through proper delay matching while maintaining bandwidth by avoiding the need for slow ramp generation and comparison operations in a single path.
Solution Approach 2:
The delay amounts in each path are dynamically adjusted based on the input voltage level through the delay amount determination circuit. This dynamic adaptation allows the system to maintain optimal signal-to-noise ratio across different input conditions while preserving bandwidth through parallel processing.
3Speed
If duplicated architecture is used, then bandwidth is improved, but linearity and reset period duration deteriorate
Solution Approach 1:
The duplicated architecture is further segmented into multiple paths within each duplication, with delay amount determination circuits that calculate optimal delays for each path. This finer segmentation maintains linearity while preserving the bandwidth benefits of the duplicated structure.
Solution Approach 2:
Delay amount determination circuits provide feedback-based optimization by calculating and adjusting delay values based on circuit performance and input conditions. This feedback mechanism corrects linearity issues in the duplicated architecture while maintaining high bandwidth operation.
4Measurement precision
If longer reset period is used, then linearity is improved, but conversion speed and bandwidth deteriorate
Solution Approach 1:
The reset operation is distributed across multiple parallel paths rather than requiring a single long reset period. Each path can be reset independently and more quickly, maintaining linearity through proper delay matching while reducing the overall conversion time and increasing bandwidth.
Data Source
AI summary
An example apparatus includes programmable circuitry configured to: provide a sample signal, a time amplification (TA) signal, and a kick signal to sample and conversion circuitry; sample a differential signal for a first amount of time-based on the sample signal; charge a first capacitor for a second amount of time-based on the first kick signal; after the first amount of time and the second amount of time, charge a second capacitor, the charging based on the first TA signal, the charging to cause a falling edge in a first delay signal; and generating, a rising edge in the delay signal based on the falling edge of the O_RST signal.