Vertical Transport FET Air-Gap Spacer Parasitic Capacitance
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Solution Overview
Problem
Vertical transport field-effect transistors (VTFETs) face challenges in reducing parasitic capacitance, which limits their potential for denser circuit layouts and improved performance compared to standard lateral FET structures.
Innovation Solution
A method for fabricating a VTFET with a faceted top source/drain region and an open gap top spacer is developed, involving a semiconductor fin structure with a gate dielectric layer, conductive gate electrode, and a sacrificial material that forms air-gaps between the top source/drain region and the dielectric liner, reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional vertical transport FET structure is used, then the circuit footprint is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent introduces air gaps (porous structure) between the top source/drain region and the dielectric liner to reduce parasitic capacitance. The air gap acts as a low-dielectric constant region that decreases the capacitive coupling between conductive elements, thereby reducing parasitic effects while maintaining the compact vertical structure.
Solution Approach 2:
The patent uses an intermediate air gap region as a mediator between the top source/drain region and the dielectric liner. This intermediate space reduces direct capacitive coupling by introducing a low-k environment, effectively decreasing parasitic capacitance without requiring additional complex structures.
2Ease of manufacture
If the top source/drain region is directly contacted to the dielectric liner, then manufacturing is simplified, but parasitic capacitance increases
Solution Approach 1:
The patent performs preliminary action by forming air gaps during the epitaxial growth process of the top source/drain region. The air gaps are created in-situ before subsequent manufacturing steps, eliminating the need for additional spacer formation processes while achieving the desired capacitance reduction.
Solution Approach 2:
The epitaxial growth process automatically creates air gaps between the top source/drain region and the dielectric liner through self-alignment mechanisms. The growing crystal structure naturally forms the gap configuration without requiring external intervention or complex patterning steps.
3Object-generated harmful factors
If a faceted top source/drain region with air-gap spacer is formed, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent replaces complex mechanical spacer formation processes with a controlled epitaxial growth process that self-organizes the air gap structure. The faceted geometry and air gaps emerge from the crystal growth mechanics rather than requiring multiple lithography and etching steps, thereby reducing overall process complexity.
Solution Approach 2:
The patent utilizes parameter changes in the epitaxial growth process (temperature, pressure, gas flow, dopant concentration) to control the formation of faceted structures and air gaps. By adjusting growth parameters, the desired complex geometry is achieved through a single process step rather than multiple fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces parasitic capacitance, enabling more compact and efficient VTFET designs with improved operational benefits, such as reduced parasitic capacitance and enhanced circuit density.
Implementation Method 1
a faceted top source/drain region is epitaxially grown on the top region of the semiconductor fin and within the cavity such that a top spacer including open gaps is formed between the top source/drain region and the dielectric liner
Data Source
AI summary
A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a top spacer including open gaps to reduce capacitance therebetween. Techniques for fabricating the transistor include using a sacrificial spacer that is selectively removed prior to growth of the top source/drain region. The top source/drain region may be confined by opposing dielectric layers.