VTFET Backside Source/Drain Contacts for Low-Resistance Power Routing

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Solution Overview

Problem

Conventional vertical-transport field-effect transistors (VTFETs) face challenges in connecting the top source/drain region to the backside power delivery network, necessitating improved methods for efficient power distribution and reduced resistance.

Innovation Solution

The implementation of increased size backside contacts to the top source/drain regions, utilizing a single contacted poly pitch (CPP) for multiple connections, and avoiding the active area layer in frontside-to-backside connections, enabling high drive and low resistance paths through a backside power delivery network.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional connection methods are used for top source/drain region, then manufacturing process is simple, but resistance is high and power distribution is inefficient

Engineering Contradiction:

Improvepower distribution efficiencyVSAvoidconnection structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent connects the top source/drain region to the backside power delivery network by routing connections through the backside of the wafer rather than through the frontside active area layer. This inversion of the connection path reduces resistance and improves power distribution efficiency without significantly increasing manufacturing complexity

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent transitions from a planar frontside connection to a three-dimensional backside connection by extending the power delivery network to the backside of the wafer. This dimensional change allows direct access to the top source/drain region through the thickness of the substrate, reducing the connection path length and resistance

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If backside contacts are made larger to reduce resistance, then resistance decreases, but area efficiency is reduced

Engineering Contradiction:

Improvecontact resistanceVSAvoidcontact area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent moves the contact area optimization to the third dimension by extending contacts through the thickness of the wafer to the backside. This allows the contact footprint on the surface to remain small while the vertical extension through the substrate provides low resistance path to the top source/drain region

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If active area layer is used in frontside-to-backside connections, then manufacturing is simpler, but resistance increases

Engineering Contradiction:

Improveconnection fabrication simplicityVSAvoidconnection resistance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent extracts the connection path from the frontside active area layer and routes it through the backside of the wafer instead. This extraction eliminates the high resistance associated with traversing the active area layer while maintaining manufacturing simplicity by using standard backside contact fabrication processes

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12557328B2Vertical-transport field-effect transistor with backside source/drain connections

Publication Date: 2026.02.17 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A VTFET is provided on a wafer. A backside power delivery network is on a backside of the wafer. A first backside contact is connected to a bottom source/drain region of the VTFET and a first portion of the backside power delivery network. A second backside contact is connected to top source/drain region of the VTFET and a second portion of the backside power delivery network.