VTFET Bottom Junction Layout for Low Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor fabrication techniques for vertical transport field effect transistors (VTFETs) face challenges in precisely controlling the proximity of the bottom junction to the channel while maintaining process window and bottom spacer reliability, often resulting in capacitance penalties.
Innovation Solution
The method involves epitaxially growing highly doped source/drain regions within a substrate, followed by precise etching and spacer deposition to form fins and bottom junctions, allowing for close proximity of the junction to the channel and reducing parasitic capacitance by decoupling the need for epitaxial region proximity from bottom spacer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bottom spacer thickness is increased to maintain reliability, then bottom spacer reliability is improved, but parasitic capacitance increases
Solution Approach 1:
The source/drain structure is segmented into multiple regions with different doping concentrations and depths. Highly doped epitaxial regions are formed at specific depths beneath the channel, creating distinct functional zones that allow the bottom spacer to be thicker for reliability while the segmented doped regions maintain electrical performance and reduce parasitic capacitance.
Solution Approach 2:
The doping profile is extended into the vertical dimension with highly doped epitaxial regions formed at controlled depths below the channel. This vertical segmentation allows the bottom spacer thickness to be increased for reliability without proportionally increasing parasitic capacitance, as the doped regions are distributed through depth rather than concentrated at a single interface.
2Productivity
If bottom junction proximity to channel is decreased to improve performance, then device performance is improved, but process control difficulty increases
Solution Approach 1:
Highly doped epitaxial regions are formed in advance at predetermined depths beneath the channel using controlled epitaxial growth and doping processes. This preliminary formation of doped regions at specific vertical positions enables subsequent processing steps to proceed with greater process windows, as the critical junction proximity is established before final structure completion.
Solution Approach 2:
The doping concentration and vertical depth parameters are optimized to create highly doped epitaxial regions at specific depths. By changing the doping parameters and epitaxial growth conditions, the junction proximity can be precisely controlled while maintaining a process window that accommodates manufacturing variations.
3Object-generated harmful factors
If highly doped epitaxial regions are formed closer to channel, then parasitic capacitance is reduced, but dielectric breakdown risk increases
Solution Approach 1:
The doped regions are segmented vertically into highly doped epitaxial regions at controlled depths, separated from the channel by undoped or lightly doped spacer regions. This segmentation allows the highly doped regions to be positioned close enough to reduce parasitic capacitance while maintaining sufficient spacing and dielectric integrity to prevent breakdown.
Solution Approach 2:
Undoped or lightly doped epitaxial regions serve as intermediary layers between the highly doped source/drain regions and the channel. These intermediary regions provide electrical isolation that prevents dielectric breakdown while allowing the highly doped regions to maintain close proximity to the channel for reduced parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-performance VTFETs with reduced parasitic capacitance and enhanced reliability by maintaining desired junction-channel proximity regardless of spacer thickness, mitigating dielectric breakdown risks.
Implementation Method 1
epitaxially growing a plurality of first lower source-drain regions within a substrate
Implementation Method 2
etching the undoped silicon layer to form fins with outer surfaces. The etching extends completely through the undoped silicon layer into the first and second lower source-drain regions
Data Source
AI summary
Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.