Vertical Transport FET Bottom Source-Drain Epitaxial Structures
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Solution Overview
Problem
Conventional semiconductor fabrication techniques are reaching limits in scaling down device sizes, particularly for vertical transport field-effect transistors (VTFETs), which hinders further miniaturization and performance enhancement in integrated circuit devices.
Innovation Solution
The development of techniques for forming vertical transport field-effect transistor structures with straight fin cut profiles and varying contact distances to bottom source/drain regions, utilizing sacrificial silicon germanium (SiGe) material for selective removal, enabling the creation of a vertical transport field-effect transistor structure with a bottom source/drain epitaxial layer of periodic varying height and contact portions on the epitaxial layer at different heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional semiconductor fabrication techniques are used, then manufacturing processes are simple and well-established, but device scaling is reaching limits and cannot achieve further miniaturization
Solution Approach 1:
The fabrication process is divided into distinct segments: forming sacrificial dummy fins, growing epitaxial layers with specific doping, selective removal of dummy fins, and forming bottom source/drain regions. This segmentation allows each step to be optimized independently, enabling advanced device scaling while maintaining manufacturing control.
Solution Approach 2:
Sacrificial dummy fins are formed in advance before the actual device fabrication. These dummy fins serve as placeholders that guide subsequent epitaxial growth and are selectively removed later. This preliminary action enables precise control over the final device geometry and source/drain positioning, achieving miniaturization with controlled complexity.
2Productivity
If device size is reduced for miniaturization, then density and performance improve, but conventional fabrication techniques cannot achieve further scaling
Solution Approach 1:
Different regions of the semiconductor structure receive different treatments: dummy fin regions are formed with sacrificial material while active device regions receive standard processing. The epitaxial layers are grown with specific doping concentrations in different zones. This local differentiation enables high device density through precise spatial control of material properties and device geometry.
Solution Approach 2:
Sacrificial dummy fins act as intermediary structures that facilitate the fabrication process. They are formed temporarily to guide epitaxial growth, then selectively removed to create the final device structure. This intermediary approach enables complex geometries and high density that would be difficult to achieve with direct fabrication methods.
3Use of energy by moving object
If device size is reduced, then power consumption decreases, but fabrication precision requirements increase
Solution Approach 1:
The epitaxial growth process is self-aligned to the dummy fin structures. The dummy fins automatically define the growth regions and boundaries, eliminating the need for additional alignment steps. This self-service approach maintains high manufacturing precision even as device dimensions are reduced, while the resulting miniaturized devices consume less power.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for further device scaling, improved density, performance, and reduced power consumption in integrated circuit devices, overcoming the limitations of conventional fabrication techniques.
Implementation Method 1
an epitaxial layer is formed adjacent a bottom portion of the at least one vertical fin
Implementation Method 2
The sacrificial semiconductor layer is selectively removed with respect to the epitaxial layer
Data Source
AI summary
A semiconductor structure comprises at least one vertical fin, an epitaxial layer adjacent a bottom portion of the at least one vertical fin, wherein the epitaxial layer comprises a plurality of different heights, and a contact structure disposed on the epitaxial layer. The contact structure is disposed on respective surfaces of the epitaxial layer at the plurality of different heights. The epitaxial layer comprises a bottom source/drain region of at least one vertical transport field-effect transistor.