Vertical Transistor Fin Self-Aligned Anchor for Source/Drain

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Solution Overview

Problem

Conventional VTFET manufacturing processes result in small volume epitaxial source/drain regions being formed away from the bottom of the channel region, reducing mechanical stability and performance, especially for single fin devices.

Innovation Solution

A method involving the formation of fins with a C-shaped configuration and a sacrificial layer to create a self-aligned anchor for epitaxial region growth under the fins, maintaining mechanical stability and increasing the effective width without increasing cell height, allowing for bottom source/drain regions to be formed directly under the fin channel regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional VTFET manufacturing processes are used, then source/drain regions can be formed, but the epitaxial source/drain regions have small volume and are formed away from the bottom of the channel region, reducing device performance

Engineering Contradiction:

Improveposition of epitaxial source/drain regionsVSAvoiddevice performance

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

A sacrificial layer is formed on the substrate before forming the fins. This sacrificial layer serves as a preliminary structure that enables subsequent formation of bottom source/drain regions at the correct position under the channel region, solving the positioning problem of epitaxial source/drain regions

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The sacrificial layer acts as an intermediary structure during manufacturing. It provides a template and support structure that guides the formation of bottom source/drain regions, ensuring they are positioned correctly under the channel region. After serving its purpose, the sacrificial layer is removed

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If source/drain regions are formed under fin channel regions, then device performance improves, but mechanical stability of the fins is reduced

Engineering Contradiction:

Improvedevice performanceVSAvoidmechanical stability of fins

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The sacrificial layer provides beforehand cushioning and mechanical support during the manufacturing process. It cushions and supports the fin structure while bottom source/drain regions are being formed, preventing mechanical instability. After forming the source/drain regions, the sacrificial layer is removed

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If fins are formed with increased effective width, then device performance improves, but cell height increases

Engineering Contradiction:

Improvedevice performanceVSAvoidcell height

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The invention introduces bottom source/drain regions in the vertical dimension under the channel region. This dimensional change allows increasing the effective width of fins without increasing cell height, as the additional current path is created in the vertical direction rather than lateral expansion

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the mechanical stability of fins and improves the performance of VTFETs by forming bottom source/drain regions under the fin channel regions, increasing the effective width of fins and maintaining the structural integrity during the manufacturing process.

Implementation Method 1

The sacrificial layer is removed from the space between the first fin and the second fin after forming the epitaxial region

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

an epitaxial region is formed under remaining portions of the first and second fins

Methodology Applied

Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11646362B2Vertical transport field-effect transistor structure having increased effective width and self-aligned anchor for source/drain region formation

Publication Date: 2023.05.09 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate. The plurality of fins each include a first portion having a first width, and a second portion having a second width greater than the first width. The method also includes forming a sacrificial layer on the substrate in a space between a first fin and a second fin of the plurality of fins, wherein the first fin and the second fin correspond to a vertical transistor. In the method, lower portions of the first and second fins are removed, and an epitaxial region is formed under remaining portions of the first and second fins. The sacrificial layer is removed from the space between the first fin and the second fin after forming the epitaxial region.