VTFET Fin Height Control With Asymmetric Bottom Epitaxy
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Solution Overview
Problem
Current VTFET manufacturing processes face challenges in achieving precise fin height control and forming abrupt junctions, leading to potential resistance issues and non-uniformities in fin height and width.
Innovation Solution
The method involves forming a vertical transport field-effect transistor (VTFET) with a bottom source/drain epitaxial layer having an asymmetric profile, where the fin height is defined by the initial epitaxial layer height, allowing for accurate fin height control and direct placement of the junction under the channel, enabling the formation of an abrupt junction and improved resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etch depth and sigma etching processes are used to form VTFET devices, then the device can be manufactured using conventional processes, but the fin height control precision deteriorates and abrupt junctions cannot be achieved
Solution Approach 1:
The bottom source/drain epitaxial layer is formed in advance with a predetermined asymmetric profile before fin formation. This preliminary action defines the fin height through the epitaxial layer thickness rather than through subsequent etching processes, enabling precise fin height control while maintaining conventional manufacturing approaches
Solution Approach 2:
The invention changes the fundamental parameter used to define fin height from etch depth to epitaxial layer thickness. By controlling the thickness of the bottom source/drain epitaxial layer during the epitaxial growth process, precise fin height control is achieved while simultaneously achieving abrupt junctions that were not possible with etching-based methods
2Manufacturing precision
If conventional etching processes are used, then the manufacturing process remains simple, but the junction abruptness deteriorates resulting in non-abrupt junctions
Solution Approach 1:
The bottom source/drain epitaxial layer is formed with an asymmetric profile where the first side is aligned with the fin channel while the second side extends beyond it. This asymmetric configuration enables the formation of abrupt junctions on one side while maintaining proper device structure, resolving the contradiction between junction abruptness and structural requirements
Solution Approach 2:
The asymmetric epitaxial layer profile provides different characteristics at different locations: on the first side it aligns with the fin channel for proper device operation, while on the second side it extends beyond to create abrupt junctions. This local differentiation achieves both structural integrity and junction abruptness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures precise fin height control and direct junction placement under the channel, enhancing the resistance and performance of VTFET devices by maintaining consistent fin height and width throughout the manufacturing process.
Implementation Method 1
forming a bottom source/drain (S/D) epitaxial layer
Data Source
AI summary
A semiconductor device includes: a vertical transport field-effect transistor (VTFET) device including a bottom source/drain (S/D) epitaxial layer, a vertical fin channel formed on the bottom S/D epitaxial layer, and a top S/D epitaxial layer formed on the vertical fin channel. The bottom S/D epitaxial layer has an asymmetric profile in cross-section where a first side of the vertical fin channel is aligned with a first side of the bottom S/D epitaxial layer, and the bottom S/D epitaxial layer has a stepped profile that extends beyond a second edge of the vertical fin channel.