Fin Length Variation Reduction in VTFET Patterning
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Solution Overview
Problem
Semiconductor manufacturing methods using single EUV exposure photolithography result in significant length variations of fins, leading to performance issues in vertical field effect transistors (VTFETs) due to the inability to meet performance variation targets.
Innovation Solution
A method involving self-aligned double patterning (SADP) and multiple mask layers to form slice walls and fill mask patterns, followed by trim mask patterns, which allows for precise control over fin lengths by aligning mask patterns perpendicular to the fin direction, thereby reducing length variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single EUV exposure photolithography is used for FH patterning, then the process is simple and fast, but the fin length variation exceeds tolerable range
Solution Approach 1:
The patent divides the single patterning step into multiple sequential patterning steps: first forming initial slice walls, then forming trim slice walls, and finally forming the FH mask pattern. This segmentation allows each step to contribute to reducing the cumulative length variation, with the trim slice walls specifically designed to compensate for variations introduced in earlier steps.
Solution Approach 2:
The patent performs preliminary actions by forming slice walls and trim slice walls before the final FH patterning step. These preliminary structures serve as self-aligned masks that pre-compensate for expected length variations, ensuring that the final fin lengths fall within the tolerable range even though multiple steps are involved.
2Manufacturing precision
If multiple mask layers and slice walls are formed to reduce fin length variation, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent employs self-aligned patterning where each subsequent mask pattern is automatically positioned relative to previous structures without requiring additional alignment steps. The slice walls and trim slice walls serve as self-aligned references for subsequent patterning steps, eliminating the need for complex external alignment procedures and reducing process complexity despite multiple patterning steps.
Solution Approach 2:
The patent merges multiple functions into the slice wall and trim slice wall structures: they serve simultaneously as spacers, masks, and alignment references for subsequent patterning steps. This consolidation reduces the number of separate process components needed and simplifies the overall process flow while maintaining high precision.
3Reliability
If multiple patterning steps are used to minimize fin length variation, then VTFET performance consistency is improved, but manufacturing time increases
Solution Approach 1:
The patent maintains continuity of useful action by ensuring that each patterning step builds directly on the previous step without interruption or re-alignment. The self-aligned nature of the process allows continuous progression through the patterning sequence, minimizing idle time and maintaining high productivity despite multiple steps being involved.
Data Source
AI summary
A method for defining a length of a fin including forming a plurality of first slice walls on a mask material layer, which is provided over the fin, using a plurality of hard mask patterns, providing a plurality of fill mask patterns self-aligned with respect to the plurality of first slice walls to expose one or more select areas between one or more pairs of adjacent ones of the plurality of first slice walls, and providing a trim mask pattern including one or more openings and self-aligned with respect to the plurality of second slice walls to expose one or more of the plurality of first slice walls may be provided.