Amorphous Silicon Liner for VTFET Gate Metal Protection

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Solution Overview

Problem

The growth of silicon nitride and other encapsulation layers during the fabrication of vertical transport field-effect transistors (VTFETs) can impair the reliability of these transistors, leading to potential device function impairment.

Innovation Solution

A method involving the conformal deposition of an amorphous encapsulation layer, such as amorphous silicon or amorphous silicon carbide, at temperatures of 400°C or less, which forms a continuous film on the gate metal layer, preventing nitridation or oxidation of the work function metal layers and enhancing the reliability of VTFETs by protecting them from encapsulation layer deposition-related damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If silicon nitride and other encapsulation layers are grown during VTFET fabrication, then device protection and insulation are improved, but metal layer nitridation or oxidation occurs causing reliability degradation

Engineering Contradiction:
Improvedevice reliabilityVSAvoidmetal layer nitridation or oxidation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An amorphous silicon or amorphous silicon carbide liner layer is deposited between the metal gate layer and the silicon nitride encapsulation layer. This intermediate liner acts as a barrier that prevents nitrogen and oxygen from the encapsulation layer from diffusing into and damaging the metal gate layer, thereby eliminating the harmful nitridation and oxidation effects while still allowing the encapsulation layer to provide its protective and insulating functions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate structure is designed as a composite multi-layer system consisting of the metal gate layer combined with the amorphous silicon or amorphous silicon carbide liner layer. This composite structure leverages the beneficial properties of each material: the metal provides gate functionality while the amorphous silicon/silicon carbide liner provides protection against nitridation and oxidation, resulting in a reliable integrated structure that withstands encapsulation layer deposition.

Inventive Principle:
Principle #40Composite materials

2Strength

If encapsulation layers are deposited to protect VTFET structures, then structural protection is improved, but device function impairment occurs due to nitridation or oxidation

Engineering Contradiction:
Improvestructural protectionVSAvoiddevice function reliability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The amorphous silicon or amorphous silicon carbide liner serves as a protective intermediary layer that allows the encapsulation structure to provide mechanical and chemical protection without causing nitridation or oxidation of the underlying metal gate. This liner enables the encapsulation layer to fulfill its protective function while preventing harmful chemical interactions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The amorphous silicon or amorphous silicon carbide liner creates an inert chemical environment between the reactive metal gate layer and the silicon nitride encapsulation layer. This inert barrier prevents nitrogen and oxygen from reaching the metal gate, effectively creating a chemically protected zone that maintains device function reliability while allowing structural protection.

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach protects the underlying metal layers from nitridation or oxidation, thereby enhancing the operational reliability and stability of VTFETs, ensuring consistent device performance.

Implementation Method 1

An amorphous encapsulation layer is conformally deposited at a temperature of about four hundred degrees Centigrade or less on the first structure. The amorphous encapsulation layer comprises amorphous silicon, amorphous silicon carbide, amorphous germanium, or amorphous silicon germanium and forms a continuous film on the gate metal layer.

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS10741663B1Encapsulation layer for vertical transport field-effect transistor gate stack
Publication Date: 2020.08.11 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10741663B1 patent drawing
  • US10741663B1 patent drawing
  • US10741663B1 patent drawing

AI summary

A vertical transport field-effect transistor includes gate metal protected by a conformal encapsulation layer. Techniques for fabricating the transistor include depositing the conformal encapsulation layer over the gate metal prior to depositing an additional encapsulation layer such as a nitride layer. The conformal encapsulation layer protects the gate metal during deposition of the additional encapsulation layer, thereby avoiding oxidation or nitridation of the gate metal. The conformal encapsulation layer may be an amorphous silicon layer deposited at relatively low temperature.