VTFET Gate Patterning With WFM Encapsulation Against Pattern Collapse
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Solution Overview
Problem
As semiconductor devices, particularly vertical transport field-effect transistors (VTFETs), are scaled down, there is a risk of electrical shorting between adjacent devices due to the high aspect ratio of device components, which can lead to pattern collapse during the manufacturing process, especially in the organic planarization layer (OPL) of VTFET pillars.
Innovation Solution
The implementation of a semiconductor device fabrication method that includes forming a bottom epitaxial layer, a gate stack with a work function metal (WFM) layer, and interlayer dielectric (ILD) layers, with a WFM encapsulation layer between the ILD layers to stabilize the structure and prevent pattern collapse by maintaining separation between adjacent VTFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If VTFET devices are scaled down to smaller dimensions, then device density and integration are improved, but electrical shorting between adjacent devices occurs due to high aspect ratio
Solution Approach 1:
The patent introduces an interlayer dielectric (ILD) material as an intermediary substance between adjacent VTFET pillars. This ILD layer physically separates the high-aspect-ratio pillars, preventing electrical shorting while allowing the pillars to maintain their high-density vertical configuration. The intermediary material acts as a barrier that enables continued scaling without compromising electrical isolation.
Solution Approach 2:
The patent transitions from lateral separation to vertical separation by introducing the ILD layer in the vertical dimension between pillars. Instead of increasing lateral pitch to prevent shorting, the solution adds a vertical dielectric layer that provides isolation while maintaining the compact lateral footprint, thus enabling higher device density without sacrificing reliability.
2Productivity
If device components have high aspect ratio to achieve vertical transport, then current flow efficiency is improved, but pattern collapse occurs during manufacturing
Solution Approach 1:
The patent applies the cushioning principle by forming the interlayer dielectric layer beforehand to provide structural support and stabilization during the manufacturing process. This pre-formed dielectric cushion prevents pattern collapse of the high-aspect-ratio pillars during subsequent processing steps, allowing the pillars to maintain their vertical transport configuration without manufacturing defects.
Solution Approach 2:
The interlayer dielectric acts as a mediator that provides mechanical support to the high-aspect-ratio pillars during fabrication. This intermediary material prevents direct contact and potential collapse between adjacent pillars, maintaining pattern integrity throughout the manufacturing process while preserving the vertical transport architecture.
3Reliability
If lateral scaling is reduced to maintain gate length and source/drain dimensions, then device performance is preserved, but device pitch must be increased reducing density
Solution Approach 1:
The patent exploits the vertical dimension to maintain gate length and source/drain dimensions without lateral scaling. By transitioning to vertical transport architecture with current flowing perpendicular to the substrate, the device preserves its performance-critical dimensions while achieving smaller lateral pitch through the use of ILD-mediated separation, thus increasing device density without sacrificing performance.
Solution Approach 2:
The interlayer dielectric serves as an intermediary that enables reduced lateral pitch by providing electrical isolation in the vertical direction. This allows the device to maintain optimal gate and source/drain dimensions for performance while achieving higher density through closer lateral spacing, as the ILD prevents shorting between adjacent vertically-oriented devices.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer, the gate stack including a work function metal (WFM) layer, a channel fin formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed in a gate landing area over the gate stack, a second ILD layer formed in an area other than the gate landing area, and a WFM encapsulation layer formed between the first ILD layer and the second ILD layer, and formed on sidewalls of the gate stack.