VTFET MOL Cross-Connection Layout for Smaller Logic Cells
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Solution Overview
Problem
Integrated circuit (IC) designs face challenges in reducing chip size without compromising device performance due to maximum wiring and device density limitations, necessitating improved Middle-of-Line (MOL) design flexibility.
Innovation Solution
The implementation of a system and method for forming semiconductor structures using vertical transport FET devices (VTFETs) with flexible MOL structures, including cross-connecting conductors formed below the M1 line level, utilizing damascene and subtractive etch processes to create conductive contact structures that enhance cell size reduction and wiring flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If wiring and device density at line levels is increased to reduce chip size, then chip area is reduced, but device performance is adversely affected due to reaching maximum density limits
Solution Approach 1:
The patent introduces Middle-of-Line (MOL) contact structures formed within the inter-level dielectric stack at intermediate levels between traditional metal layers. This adds a new dimensional layer for interconnectivity, allowing signals to be routed through vertical contacts embedded in the dielectric stack rather than only through planar metal layers, thereby reducing chip area without compromising device performance
2Ease of manufacture
If traditional IC design with fixed wiring levels is used, then manufacturing is simpler, but MOL design flexibility is limited and cell size reduction is hindered
Solution Approach 1:
The patent segments the inter-level dielectric stack into multiple levels and forms conductive contact structures at specific intermediate levels within the stack. This segmentation allows independent formation and routing of MOL contacts at different heights, providing design flexibility for cross-connecting conductors while maintaining compatibility with standard manufacturing processes
Solution Approach 2:
The patent introduces intermediate MOL contact structures as mediators between traditional metal layers. These contact structures are formed within the inter-level dielectric stack and provide additional routing pathways for signals, enabling flexible circuit design and cell size reduction without requiring changes to the fundamental manufacturing process flow
Data Source
AI summary
Integrated circuits and related logic circuits and structures employing VTFET logic devices. In particular, during middle-of-line (MOL) processing, method steps are employed for forming two-level MOL contact connector structures below first (M1) metallization level wiring formed during subsequent BEOL processing. Using damascene and subtractive metal etch techniques, respective MOL contact connector structures at two levels are formed with a second level above a first level contact. These contact connector structures at two levels below M1 metallization level can provide cross-connections to VTFET devices of logic circuits that enable increased scaling of the logic circuit designs, e.g., especially for multiplexor circuit layouts due to wiring access. The flexible MOL cross-connections made below M1 metallization level provides for much improved M1 and M2 wirability and enable semiconductor circuit layouts that allow for improved cell size reduction without creating significant connection issues at high wiring levels thereby increasing circuit design flexibility.