VTFET Output Jumper Layout for Lower Via Resistance
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Solution Overview
Problem
Existing semiconductor device chip architectures face challenges in increasing transistor density while minimizing surface area, as horizontal layouts occupy significant space and current technologies lack efficient jumper configurations in vertical transport field effect transistors (VTFETs).
Innovation Solution
Implementing a semiconductor device structure with multiple parallel V0/M1/V1 jumper sequences and metallization tracks, utilizing semi-damascene processes to form vias and jumpers, which reduce via resistance and optimize circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If horizontal layout is used for transistors, then current flow and gate connection are simplified, but transistor density increases surface area occupation
Solution Approach 1:
The patent transitions from horizontal (2D) transistor layout to vertical (3D) transistor stacking, where multiple transistor layers are arranged perpendicular to the substrate. This dimensional change allows current flow and gate connections to extend through the vertical dimension, significantly reducing the chip surface area occupied by transistors while maintaining manufacturing feasibility through adapted fabrication processes.
2Area of stationary object
If vertical transport FET structure is implemented, then transistor density increases and surface area reduces, but via resistance increases due to longer current paths
Solution Approach 1:
The patent divides the vertical current path into multiple shorter via segments by introducing intermediate metallization layers (M1, M2, etc.) and jumper structures. Instead of a single long via path, the current flows through a series of shorter vias connected by horizontal metallization segments, reducing the resistance of each individual via and optimizing overall electrical performance.
Solution Approach 2:
The patent introduces intermediate metallization layers and jumper structures as mediator elements between the substrate and upper transistor layers. These intermediaries provide low-resistance horizontal connection paths that break up the vertical current flow into manageable segments, reducing cumulative via resistance while enabling continued vertical scaling for high density.
3Reliability
If multiple parallel V0/M1/V1 jumper sequences are added, then via resistance reduces and circuit performance improves, but device complexity increases
Solution Approach 1:
The patent designs the metallization layers (M1, M2, etc.) and jumper structures to serve multiple functions: they provide horizontal current distribution paths, act as connection intermediaries between vertical via segments, and enable parallel current flow routes. This multi-functionality reduces the need for separate dedicated structures, managing complexity while achieving low resistance and high performance.
Data Source
AI summary
A semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.