Self-Aligned Poly Silicide Gate Stack for VTFET Threshold Stability
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Solution Overview
Problem
The scaling of silicon MOSFETs to theoretically predicted miniaturization limits is hindered by the inability to simply shrink all device features, and forming reliable gate stacks for vertical transport field-effect transistors (VTFETs) is challenging due to high thermal budgets and oxygen diffusion issues, making it difficult to achieve optimal inversion layer thickness and threshold voltage.
Innovation Solution
The formation of self-aligned metal gates with poly silicide for VTFETs involves creating an interfacial layer, a high-k dielectric layer, a metal gate layer, a silicon layer, and a silicide layer, with an oxygen barrier layer to prevent oxygen diffusion and a self-alignment spacer hard mask to define the poly silicide gates, facilitating the formation of reliable gate stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal gate layers are formed for VTFETs, then device scaling benefits are improved, but gate electrode resistivity increases and inversion layer thickness becomes unstable
Solution Approach 1:
The patent forms a composite gate electrode structure comprising a metal gate layer (e.g., titanium nitride, tantalum nitride) combined with a polysilicon layer. This composite structure leverages the low resistivity of metals and the stable electrical characteristics of polysilicon to simultaneously achieve low gate electrode resistivity and stable inversion layer thickness, resolving the technical contradiction between device scaling benefits and electrical stability.
Solution Approach 2:
The patent employs silicidation processing to transform the polysilicon layer into a silicide layer (e.g., nickel silicide, cobalt silicide) with controlled stoichiometry and crystal structure. By adjusting silicidation parameters such as temperature, time, and metal layer composition, the gate electrode achieves optimized electrical properties including reduced resistivity and stabilized inversion layer thickness, enabling continued device scaling.
2Power
If high-k dielectric layers are formed surrounding channel stacks, then transistor performance is improved, but oxygen diffusion issues arise affecting threshold voltage
Solution Approach 1:
The patent introduces an oxygen barrier layer (e.g., silicon nitride, silicon oxynitride) between the high-k dielectric layer and the channel stack. This intermediary layer prevents oxygen diffusion from the high-k dielectric into the channel region, thereby stabilizing the inversion layer thickness and threshold voltage while preserving the high transistor performance enabled by the high-k dielectric.
3Productivity
If device features are shrunk to miniaturization limits, then integration density is improved, but manufacturing precision becomes difficult to maintain
Solution Approach 1:
The patent employs self-aligned fabrication techniques where the metal gate layer and polysilicon layer are deposited conformally on the channel stacks, and the oxygen barrier layer is formed in advance to prevent oxygen diffusion. This preliminary structuring ensures precise gate stack formation at miniaturized dimensions without requiring additional alignment steps, thereby maintaining manufacturing precision while achieving high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved device scaling benefits for VTFETs by reducing gate electrode resistivity and stabilizing the inversion layer thickness and threshold voltage, overcoming the limitations of existing FinFET technologies.
Implementation Method 1
performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer
Implementation Method 2
an oxygen barrier layer to prevent oxygen diffusion
Data Source
AI summary
A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).