SRAM Bitcells with Vertical-Transport FETs and Trench Isolation
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Solution Overview
Problem
Current SRAM bitcell structures face challenges in efficiently integrating vertical-transport field-effect transistors (VTFETs) to enhance data storage and access operations, particularly in achieving concurrent read and write capabilities while maintaining electrical isolation and conductivity type alignment.
Innovation Solution
The structure and method involve forming a two-port SRAM with vertically projecting fins and strategically aligned source/drain regions, using trench isolation and ion implantation to define active device regions, and forming VTFETs with fins and gates arranged in a gate-all-around configuration to enable efficient data storage and access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical-transport field-effect transistors (VTFETs) are integrated into SRAM bitcells to enhance data storage and access operations, then data storage efficiency and access capabilities are improved, but device structure complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar horizontal current transport to vertical current transport through semiconductor fins. The channel region is arranged vertically between source and drain regions, with current flowing in the vertical direction relative to the substrate surface, thereby increasing the effective channel area without proportionally increasing the lateral footprint of the device.
Solution Approach 2:
The gate electrode is configured to wrap around the semiconductor fin in a gate-all-around configuration, with the gate surrounding the fin on multiple sides. This nested arrangement maximizes the gate's control over the channel while minimizing the lateral space required, thereby improving device efficiency without proportionally increasing complexity.
2Ease of operation
If VTFETs are used to enable concurrent read and write operations in two-port SRAM, then access capabilities are enhanced, but maintaining electrical isolation between adjacent devices becomes more challenging
Solution Approach 1:
The patent divides the semiconductor structure into discrete fins separated by isolation regions. Each fin serves as an independent vertical channel for a VTFET, with source and drain regions laterally arranged between adjacent fins. This segmentation provides natural electrical isolation between adjacent VTFETs while maintaining vertical transport efficiency.
Solution Approach 2:
Isolation regions are introduced as intermediary structures between adjacent active device regions. These isolation regions electrically separate the source/drain regions of adjacent VTFETs, preventing unwanted current leakage and maintaining electrical isolation reliability while allowing dense packing of vertical transport devices.
3Power
If fins are arranged vertically with source/drain regions laterally positioned between adjacent fins, then manufacturing precision requirements increase, but current flow efficiency is improved
Solution Approach 1:
The patent forms the semiconductor fins and source/drain regions in a predetermined sequence using ion implantation through masks. The source and drain regions are implanted laterally between adjacent fins before final gate formation, establishing the correct spatial relationships early in the manufacturing process and simplifying subsequent alignment steps.
Solution Approach 2:
The patent combines multiple fabrication steps into integrated processes. Ion implantation simultaneously defines both the source/drain regions and the fin structures, while the gate-all-around formation process concurrently creates the gate electrode and establishes electrical connections. This merging reduces the total number of alignment-critical steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the effective integration of VTFETs in SRAM bitcells, enabling concurrent read and write operations while maintaining electrical isolation, thereby improving data storage efficiency and access capabilities.
Implementation Method 1
implanting the first active device region and the second active device region with ions of a first conductivity type. After forming the implantation mask, the first active device region and the second active device region are implanted with ions of a second conductivity type
Data Source
AI summary
Structures for a static random access memory (SRAM) bitcell and methods for forming a SRAM bitcell. The SRAM includes a storage element with a first pull-up (PU) vertical-transport field-effect transistor (VTFET) having a first bottom source/drain region and a fin projecting from the first bottom source/drain region, and a second pull-up (PU) VTFET with a second bottom source/drain region and a fin projecting from the second bottom source/drain region. The fin of the first PU VTFET is arranged over a first active region in which the first bottom source/drain region is centrally arranged, and the fin of the second PU VTFET is arranged over a second active region in which the second bottom source/drain region is centrally arranged. The second source/drain region is aligned with the first bottom source/drain region. A read port may be connected with the storage element, and may also be formed using VTFETs.