VTFinFET Bottom Source/Drain Structure for Dopant Diffusion Control
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Solution Overview
Problem
Current methods for fabricating vertical transport fin field effect transistors (VTFinFETs) face challenges in forming effective bottom source/drain structures that can sustain high thermal drive temperatures and control dopant diffusion, leading to suboptimal resistance and performance.
Innovation Solution
The method involves forming vertical fins on a substrate, creating a support pillar and cavity, growing a bottom source/drain layer, and forming a diffusion barrier layer to block dopant diffusion, with specific dopant concentrations and heat treatments to form extension regions, enhancing the bottom source/drain resistance and dopant control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bottom source/drain structures are used in VTFinFET fabrication, then the manufacturing process is simpler, but the resistance is suboptimal and dopant diffusion cannot be controlled
Solution Approach 1:
The bottom source/drain structure is segmented into multiple functional regions: the bottom source/drain region, extension regions, and necked region. This segmentation allows each region to have optimized dopant concentrations and diffusion characteristics, improving overall device performance while maintaining manufacturability through standardized process modules.
Solution Approach 2:
Different regions of the bottom source/drain structure are assigned different dopant concentrations and material compositions. The extension regions have higher dopant concentrations to reduce resistance, while the necked region has lower concentration to control diffusion. This local quality variation optimizes both electrical performance and dopant control without requiring complete structural redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the resistance of the bottom source/drain structure and controls dopant diffusion, leading to enhanced performance and reliability of VTFinFET devices, suitable for various logic and memory applications.
Implementation Method 1
forming a diffusion barrier layer on the bottom source/drain layer that fills in the cavity to block diffusion of dopants from the bottom source/drain layer above a necked region in the support pillar
Implementation Method 2
Heat treatment can be performed to form extension regions in the plinth and support pillar
Data Source
AI summary
A method of forming a vertical transport fin field effect transistor device is provided. The method includes forming vertical fins on a substrate, depositing a protective liner on the sidewalls of the vertical fins, and removing a portion of the substrate to form a support pillar beneath at least one of the vertical fins. The method further includes etching a cavity in the support pillar of the at least one of the vertical fins, and removing an additional portion of the substrate to form a plinth beneath the support pillar of the vertical fin. The method further includes growing a bottom source/drain layer on the substrate adjacent to the plinth, and forming a diffusion plug in the cavity, wherein the diffusion plug is configured to block diffusion of dopants from the bottom source/drain layer above a necked region in the support pillar.