Vertical Trench MOSFET Polysilicon Sinker Formation
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Solution Overview
Problem
Existing methods for manufacturing vertical trench MOS (VTMOS) devices face challenges in achieving uniform dopant diffusion and low resistivity for thick epitaxial layers, leading to high ON-state resistance, especially when the epitaxial layer thickness exceeds 3-4 μm, and result in defective surface growth and high production costs.
Innovation Solution
A method involving the growth of a polycrystalline silicon region using a silicon oxide seed, allowing for high-temperature processing and uniform dopant diffusion, which forms a conductive path with reduced resistivity by extending through the epitaxial layer and providing a transition zone for efficient dopant distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional implantation and thermal diffusion methods are used for thick epitaxial layers (>3-4 μm), then the conductive path may not reach the drain region, but using higher implantation energies or multiple implantations increases process complexity and cost
Solution Approach 1:
A polycrystalline silicon seed layer is formed in advance at the bottom of the trench structure before the epitaxial growth step. This preliminary action creates a favorable environment for fast dopant diffusion during subsequent processing, eliminating the need for multiple high-energy implantation steps and simplifying the overall manufacturing process while ensuring reliable conductive path formation through thick epitaxial layers.
2Productivity
If high temperatures (>1100° C.) are used for epitaxial layer growth to achieve adequate thickness in compatible production times, then production volume compatibility is improved, but polysilicon seed fails to form and highly defective monocrystalline silicon regions are formed instead
Solution Approach 1:
The invention changes the temperature parameter for epitaxial layer growth to a range of 700-800° C., which is lower than conventional temperatures. This parameter change enables the polysilicon seed to successfully form a polysilicon column during epitaxial growth, ensuring reliable conductive path formation while maintaining acceptable production efficiency through optimized process conditions.
3Speed
If polysilicon column growth is attempted at high temperatures for fast dopant diffusion, then dopant diffusion speed is improved, but defective monocrystalline silicon regions are formed and surface deflection occurs
Solution Approach 1:
The invention changes the temperature parameter to 700-800° C. during epitaxial growth, which enables controlled polysilicon column formation from the seed layer. This temperature optimization ensures uniform dopant diffusion through the polycrystalline structure while maintaining surface uniformity and preventing the formation of defective regions that occur at higher temperatures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a lower resistivity drain sinker region with improved dopant distribution and reduced ON-state resistance, enhancing device performance, power efficiency, and reducing thermal dissipation.
Implementation Method 1
A method involving the growth of a polycrystalline silicon region using a silicon oxide seed, allowing for high-temperature processing and uniform dopant diffusion
Implementation Method 2
which forms a conductive path with reduced resistivity by extending through the epitaxial layer and providing a transition zone for efficient dopant distribution
Data Source
AI summary
A method of manufacturing a vertical conduction semiconductor device comprising the steps of: forming a recess in a monocrystalline silicon substrate; forming a silicon oxide seed layer in the recess; carrying out an epitaxial growth of silicon on the substrate, simultaneously growing a polycrystalline silicon region in the seed layer and a monocrystalline silicon region in surface regions of the substrate, which surround the seed layer; and implanting dopant species in the polycrystalline silicon region to form a conductive path in order to render the second conduction terminal electrically accessible from a front side of the vertical conduction semiconductor device.