VTT Generator Chopper Circuit for Low-Power Signal Termination
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Solution Overview
Problem
In semiconductor chips, interconnect capacitance reduces signal integrity and transfer rate due to transmission line effects like distributed inductance, capacitance, and resistance, causing electrical interference and noise, especially as operating voltage decreases.
Innovation Solution
A termination voltage generator using an inverter-based chopper circuit with serially connected PMOS and NMOS transistors, coupled with a replica inverter, voltage divider, and unity gain buffer, is employed to generate and stabilize the termination voltage, reducing noise and maintaining signal integrity by adjusting transistor source voltages and using capacitance to stabilize the termination voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If operating voltage is decreased to reduce power consumption, then power consumption is reduced, but signal integrity and noise margin deteriorate
Solution Approach 1:
A termination voltage generator is introduced as an intermediary component that provides a stable reference voltage (VTT) to receivers. This mediator compensates for the degraded signal quality caused by low operating voltages by establishing a reliable voltage reference that improves noise margin and signal integrity without requiring higher operating voltages.
Solution Approach 2:
The patent changes the voltage parameter by generating a termination voltage that is a fraction of the power supply voltage (e.g., VTT = VDD/2). This parameter transformation allows the system to operate at low voltages while maintaining adequate signal swing and noise margin through proper impedance matching and voltage reference establishment.
2Speed
If interconnect capacitance increases due to transmission line effects, then signal transfer rate decreases, but interconnect capacitance cannot be reduced due to physical constraints
Solution Approach 1:
The termination voltage generator acts as a mediator that compensates for the adverse effects of interconnect capacitance. By providing a stable voltage reference and enabling proper termination, it reduces signal reflection and noise caused by capacitive coupling, thereby maintaining signal integrity and transfer rate despite the inherent capacitance of interconnect traces.
3Reliability
If termination voltage stability is improved to reduce noise, then signal integrity improves, but device complexity increases
Solution Approach 1:
The termination voltage generation function is segmented from the main signal processing path and implemented as a separate, dedicated circuit block. This segmentation allows the termination voltage generator to be optimized independently, providing stable voltage reference without complicating the main data path logic.
Solution Approach 2:
The termination voltage generator serves multiple functions: it provides impedance matching, establishes voltage reference, reduces noise, and compensates for process variations. By consolidating these functions into a single multi-functional component, the patent avoids the complexity that would result from implementing each function separately.
Data Source
AI summary
Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.


