VVC Decoder Pipeline Optimization via CCLM and Parallel Processing
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Solution Overview
Problem
Existing video coding technologies face challenges in efficiently decoding and processing advanced video features, particularly in versatile video coding (VVC) decoder pipelines, which require improved performance and area efficiency.
Innovation Solution
The enhanced video coding system leverages existing features for efficient storage and parallel computation, specifically in CCLM intra-prediction, CIIP prediction, PDPC filtering, and inter-prediction luma mapping and residual chroma scaling, to optimize performance and reduce area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If advanced video coding features (CCLM, CIIP, PDPC, LMCS) are implemented in VVC decoder pipeline, then video quality and coding efficiency are improved, but decoder complexity and area requirements increase
Solution Approach 1:
The decoder pipeline is segmented into distinct functional modules for CCLM intra-prediction, CIIP prediction, PDPC filtering, and LMCS. Each module processes specific aspects of video decoding independently, allowing complex features to be broken down into manageable segments that can be optimized separately while maintaining overall video quality.
Solution Approach 2:
The decoder pipeline is designed with multi-functional components that can handle multiple advanced video coding features through a unified architecture. The same hardware resources are utilized across different prediction and filtering modes, reducing overall decoder complexity while supporting CCLM, CIIP, PDPC, and LMCS features simultaneously.
2Productivity
If advanced video coding features are implemented in VVC decoder pipeline, then coding efficiency is improved, but area occupancy increases
Solution Approach 1:
Multiple advanced video coding features (CCLM, CIIP, PDPC, LMCS) are merged into a single integrated decoder pipeline. By combining these features in one unified processing flow, the patent achieves high coding efficiency while minimizing area occupancy through shared resources and eliminated redundancy between separate feature implementations.
Solution Approach 2:
The decoder pipeline utilizes parallel computation streams and multi-dimensional data processing to achieve high coding efficiency without proportionally increasing area occupancy. By processing multiple video features simultaneously through parallel pipelines and optimizing data flow dimensions, the system maintains high productivity while controlling hardware area requirements.
3Speed
If parallel computation is used for CCLM, CIIP, PDPC, and LMCS features, then processing speed is improved, but resource requirements increase
Solution Approach 1:
The parallel computation architecture ensures continuous processing of CCLM, CIIP, PDPC, and LMCS features without idle resource periods. Each computational unit maintains continuous useful action by processing different aspects of video decoding simultaneously, maximizing processing speed while optimizing resource utilization to avoid unnecessary resource consumption.
Data Source
AI summary
This disclosure describes systems, methods, and devices related to enhanced video coding. A device may receive encoded bitstream data of a frame with multiple tiles. The device may divide each tile into multiple coding tree units (CTUs). The device may decode Luma and Chroma pixels of each CTU using either a single-tree mode or a dual-tree mode. The device may execute a cross-component linear model (CCLM) prediction to predict Chroma pixels based on decoded Luma pixels. The device may store the decoded Luma pixels and the predicted Chroma pixels in a storage.