W-2W DAC Bulk Bias Compensation for Linear Current Pulses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional W-2W current-steering digital-to-analog converters (IDACs) used in phase-change memory devices often suffer from systematic errors, resulting in output current pulses that fail to maintain the correct shape and linearity during SET pulses, affecting the temperature gradient applied to memory storage elements.
Innovation Solution
A circuit design incorporating diode-connected MOS transistors and mirroring MOS transistors with temperature-dependent compensation signals, generated by a proportional-to-absolute-temperature current generator and voltage divider circuit, to mitigate the body effect and ensure linear output current pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If W-2W current-steering digital-to-analog converter architecture is used, then silicon area is reduced, but systematic errors occur in transistors causing incorrect output current pulse shape
Solution Approach 1:
The patent applies parameter changes by modifying the bulk terminal voltage of mirroring MOS transistors through compensation signals. By dynamically adjusting the bulk terminal parameter (voltage) based on temperature-dependent body effect compensation, the transistor threshold voltages are corrected to eliminate systematic errors in the W-2W architecture, thereby maintaining accurate output current pulse shapes while preserving the compact silicon area design
Solution Approach 2:
The patent uses copying by replicating the body effect compensation mechanism across multiple mirroring MOS transistors in the W-2W architecture. Each mirroring transistor's bulk terminal receives compensation signals that copy the temperature-dependent correction pattern, ensuring uniform error correction across all transistors and maintaining consistent output current pulse shapes throughout the circuit
2Manufacturing precision
If temperature compensation signals are applied to bulk terminals, then body effect is compensated and linearity is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a single bulk terminal compensation mechanism that serves multiple functions simultaneously. The same compensation circuit structure and signal generation approach is universally applied to all mirroring MOS transistors in the W-2W architecture, providing body effect compensation across the entire circuit through a standardized, reusable design pattern that minimizes overall complexity
Solution Approach 2:
The patent uses parameter changes by implementing temperature-dependent compensation signals that dynamically adjust the bulk terminal voltage parameter. This allows the circuit to automatically adapt to temperature variations and maintain linear current pulse output without requiring complex manual calibration or multiple discrete compensation circuits, thereby improving linearity while controlling device complexity
Data Source
AI summary
In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.