w-NAF Conversion Circuit for Low-Memory Cryptographic Processing
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Solution Overview
Problem
Existing methods for converting binary representations into redundant binary representations, such as NAF, face challenges in efficiently processing integers due to high memory usage and computational overhead, particularly in limited memory environments like cell phones, where a trade-off exists between processing speed and memory consumption.
Innovation Solution
A w-NAF conversion apparatus is designed, comprising an acceptance device, a storage device, and a shift register, which sequentially processes binary inputs to produce a w-NAF representation, allowing dynamic adjustment of w to optimize between memory usage and processing speed by varying the width of the shift register and the number of possible numerals used.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing NAF conversion methods are used to convert binary representations into redundant binary representations, then processing speed is improved, but memory consumption increases
Solution Approach 1:
The patent divides the NAF conversion process into sequential stages using a shift register that processes input bits one at a time. The conversion is segmented into discrete clock cycles where each cycle processes a portion of the input and produces a corresponding output digit, avoiding the need to load entire numbers into memory simultaneously.
Solution Approach 2:
The patent extracts only the essential state information needed for conversion by maintaining a minimal set of state variables in the shift register. Instead of storing complete intermediate results, the system extracts and retains only the necessary state bits that determine future conversion outcomes, significantly reducing memory requirements.
2Device complexity
If a fixed w-value is used in w-NAF conversion, then circuit design is simplified, but adaptability to different processing requirements is reduced
Solution Approach 1:
The patent implements a dynamic w-value mechanism where the width parameter can be adjusted based on processing requirements. The shift register and control logic are designed to accommodate variable w-values, allowing the system to adapt between different conversion modes (e.g., changing from 2-NAF to 4-NAF) without requiring complete circuit redesign.
Solution Approach 2:
The conversion apparatus is designed with universal components that can function with different w-values. The same basic circuit structure handles multiple w-NAF variants by adjusting control parameters, making the system multi-functional and adaptable to various cryptographic algorithms that require different redundancy widths.
Data Source
AI summary
According to one embodiment, a NAF conversion apparatus which converts a binary representation of an integer into a w-NAF redundant binary representation includes an acceptance device, a storage device, a shift register, and an update device. The acceptance device accepts the binary representation of the integer for every bit from lower bits. The storage device stores a state value expressed by 1 bit. The shift register stores a state value expressed by (w−1) bits. The update device determines a state of the storage device and a state of the (w−1)-bit shift register at next time, and determines a w-bit parallel output at current time by referring to a 1-bit value accepted by the acceptance device, the state value in the storage device, and the state value in the (w−1)-bit shift register.