Wafer-to-Wafer Chip Stack Yield Optimization via Defect Sorting
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Solution Overview
Problem
The Wafer to Wafer (W2W) method for manufacturing semiconductor devices, which stacks wafers before dicing, faces a cumulative increase in defect rates as the number of stacked wafers rises, leading to reduced product yield and increased costs, despite offering superior manufacturing efficiency compared to the Chip to Chip (C2C) method.
Innovation Solution
The method involves forming first and second chip stacks using the W2W method, sorting them based on defective chip counts, and combining them to achieve a desired number of non-defective chips in a third chip stack, thereby optimizing yield and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the W2W method is used to stack multiple wafers before dicing, then manufacturing efficiency is improved, but the defect rate increases cumulatively with the number of stacked wafers
Solution Approach 1:
The patent segments the stacking process into multiple batches, where each batch contains a limited number of wafers (e.g., 2-5 wafers per batch). This segmentation prevents the cumulative defect rate from becoming too high in any single batch, thereby maintaining product yield while still achieving high manufacturing efficiency through parallel processing of multiple batches.
Solution Approach 2:
The patent changes the parameter of batch size in the stacking process. By controlling the number of wafers per batch to be within a specific range (2-5 wafers), the cumulative defect rate is kept below a threshold (e.g., 5%). This parameter optimization allows the W2W method to maintain both high productivity and acceptable reliability.
2Quantity of substance
If the number of stacked wafers is increased to achieve higher integration, then the degree of integration is improved, but the defect rate rises cumulatively leading to fall in product yield
Solution Approach 1:
The patent divides the total number of chips to be stacked into multiple batches, with each batch containing a limited number of wafers. This segmentation allows the total quantity of stacked chips to increase while keeping the defect rate in each individual batch manageable, thus maintaining overall product yield.
Solution Approach 2:
The patent introduces a new dimension of batch management to the stacking process. Instead of simply increasing the number of stacked wafers in a single batch, the system organizes wafers into multiple batches along the time dimension, processing and combining them sequentially. This dimensional change allows higher integration without the cumulative defect penalty of single-batch stacking.
Data Source
AI summary
After stacking m wafers in each of which a plurality of semiconductor chips are formed, the m wafers are diced to semiconductor chips to form a first chip stack having m of the semiconductor chips stacked, and, after stacking n wafers, the n wafers are diced to semiconductor chips to form a second chip stack having n of the semiconductor chips stacked. Next, the first chip stack is sorted according to the number of defective semiconductor chips included in the first chip stack, and the second chip stack is sorted according to the number of defective semiconductor chips included in the second chip stack. Furthermore, the first chip stack or the second chip stack after sorting are combined to form a third chip stack.