Wafer Alignment Using Conductive Transmission Columns
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Solution Overview
Problem
The existing methods for aligning wafers in multichip packages are imprecise, leading to variations in the width of through silicon vias (TSVs) and affecting the reliability of electrical communication between chips, which impacts device performance.
Innovation Solution
The use of electrically or optically conductive columns that extend through the wafers, formed in selected patterns, allows for precise alignment by automated equipment that detects signals through the columns to make adjustments for accurate positioning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional alignment methods are used to align wafers, then the alignment process is simple, but the alignment precision is insufficient leading to variations in TSV width
Solution Approach 1:
The patent introduces alignment marks as intermediary reference features on each wafer that mediate the alignment process. These marks serve as intermediate reference points that enable precise positioning between wafers without requiring direct complex measurement systems, thereby improving alignment precision while managing system complexity
Solution Approach 2:
The patent replaces traditional mechanical alignment methods with optical detection systems that use alignment marks and automated imaging. This substitution of mechanical systems with optical/electronic systems enables higher alignment precision and automation, resolving the contradiction between precision and complexity
2Productivity
If wafers are aligned at the wafer level, then the process efficiency is improved, but the alignment accuracy deteriorates due to cumulative errors
Solution Approach 1:
The patent segments the alignment process into multiple hierarchical levels: coarse alignment using wafer-level marks, followed by fine alignment using die-level marks. This segmentation allows efficient wafer-level processing while achieving high precision through successive refinement stages, resolving the contradiction between productivity and precision
3Ease of manufacture
If TSVs are formed with fixed diameter, then the manufacturing process is simplified, but the alignment tolerance is reduced
Solution Approach 1:
The patent performs preliminary alignment using alignment marks before TSV formation and bonding processes. By establishing precise positional relationships in advance through mark-based alignment, the system compensates for any TSV diameter variations, allowing simplified fixed-diameter TSV fabrication while maintaining electrical communication reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise alignment of wafers, improving the reliability of electrical communication and overall device performance by ensuring accurate alignment of TSVs, thereby enhancing the reliability of vertically stacked multichip packages.
Implementation Method 1
The alignment structures are a plurality of electrically or optically conductive columns that extend completely through the die or wafer
Implementation Method 2
The alignment structures are a plurality of electrically or optically conductive columns that extend completely through the die or wafer
Data Source
AI summary
A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.