Narrow Wafer Scribe Line Alignment Mark Placement
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in minimizing scribe line width while maintaining alignment marks compatible with existing photomask alignment infrastructure, as traditional alignment marks are often too large for advanced processes, leading to increased wafer area consumption and reduced device density.
Innovation Solution
The use of alignment marks positioned at the intersection of scribe lines with dimensions greater than the scribe lines themselves, allowing for reduced scribe line width without compromising visibility at 1× magnification, utilizing conductive materials like tungsten, titanium, or gold, and corresponding reference marks on photomasks with similar dimensions for precise alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional alignment marks are used in scribe lines, then alignment compatibility with existing photomask infrastructure is maintained, but scribe line width must be increased to accommodate the alignment marks, reducing device density
Solution Approach 1:
The patent applies local quality by creating alignment marks with non-uniform dimensions - specifically, the alignment marks have a first dimension (e.g., 80-100 μm) that is larger than the scribe line width (e.g., 40-60 μm) in the orthogonal direction. This allows the alignment marks to be visible at 1× magnification for compatibility with existing photomask infrastructure, while the scribe lines themselves can be minimized to increase device density. The alignment marks are positioned at intersections of scribe lines where they locally occupy space without requiring the entire scribe line to be widened.
2Productivity
If scribe line width is reduced to increase device density, then wafer area overhead is reduced, but alignment marks become too small to be visible at 1× magnification, compromising alignment precision
Solution Approach 1:
The patent resolves this contradiction by making the alignment marks have different dimensions in different directions - the dimension parallel to the scribe line (first dimension) is made larger (80-100 μm) to ensure visibility at 1× magnification, while the dimension perpendicular to the scribe line (second dimension) is minimized to match the narrow scribe line width (40-60 μm). This allows narrow scribe lines to accommodate alignment marks that remain visible for precise alignment with existing photomask infrastructure.
Solution Approach 2:
The patent applies dimensionality change by orienting the alignment mark dimensions anisotropically - the alignment marks are designed with a primary dimension along the scribe line direction and a secondary dimension perpendicular to it. By making the primary dimension larger than the secondary dimension, the alignment marks achieve sufficient visibility for alignment purposes while fitting within the constrained width of narrow scribe lines, thus resolving the conflict between device density and alignment visibility.
3Measurement precision
If alignment marks are made larger for visibility, then alignment precision is improved, but more wafer area is consumed, reducing the number of devices per wafer
Solution Approach 1:
The patent applies local quality by concentrating the alignment mark functionality at specific locations (intersections of scribe lines) rather than requiring continuous alignment marks throughout the scribe lines. The alignment marks are made larger only in the dimension necessary for visibility (along the scribe line), while minimizing their footprint in the orthogonal direction. This localized approach maintains alignment precision without proportionally increasing the total area consumed, thereby preserving device density.
Data Source
AI summary
Methods and apparatus for front-to-back alignment using narrow scribe lines are disclosed. An apparatus is disclosed that includes a semiconductor wafer comprising a plurality of areas for the fabrication of integrated circuit devices on a device side, the integrated circuit devices arranged in rows and columns and spaced from one another by a plurality of scribe lines disposed on the semiconductor wafer in areas between the integrated circuit devices and free from integrated circuit devices; and one or more alignment marks disposed on the semiconductor wafer, the alignment marks positioned in an intersection of two of the scribe lines; wherein the scribe lines have a first minimum dimension and the one or more alignment marks have a second minimum dimension that is greater than the first minimum dimension. Methods and additional apparatus are disclosed.