Wafer Alignment Mark Structure for Visible Dielectric Layer Patterning
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Solution Overview
Problem
In semiconductor packaging, the small height difference of IC circuit layers on wafers makes alignment marks invisible under dielectric layers, leading to misalignment and reduced production efficiency, as exposure machines cannot recognize these marks after photoresist coating, necessitating reworking and disrupting continuous production.
Innovation Solution
A method is developed to form a prominent alignment mark on the wafer surface by depositing a metal layer with a thickness of at least 0.3 μm as an under-bump metallization (UBM) layer, which is exposed and used as a visible marker through photoresist removal techniques, ensuring the mark remains visible under the dielectric layer, utilizing a chromium-copper layer structure for enhanced visibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric layer is formed on the wafer surface during packaging, then the wafer structure is completed and protected, but the alignment mark becomes invisible and cannot be recognized by the exposure machine
Solution Approach 1:
The alignment mark is formed on the wafer surface before the dielectric layer is deposited. By performing the alignment mark creation in advance, the mark remains exposed and visible during the packaging process, allowing the exposure machine to recognize it without being obscured by subsequent dielectric layer formation.
Solution Approach 2:
The alignment mark is created at a specific location on the wafer surface with distinct metal material properties, differentiating it from the surrounding areas. This localized feature ensures the mark remains detectable even when other areas are covered by dielectric layers, as it maintains its unique optical and physical characteristics.
2Shape
If the height difference of IC circuit layers is small (about 0.1 μm), then the wafer structure is compact, but the alignment mark becomes invisible after photoresist coating
Solution Approach 1:
The alignment mark is formed with a metal material and specific thickness that creates a height difference greater than 0.1 μm, making it protrude from the wafer surface. This parameter change in height and material composition ensures the mark remains visible and detectable by the exposure machine even when the overall wafer structure maintains compact dimensions.
3Productivity
If the alignment mark is covered by photoresist and dielectric layer, then continuous production is maintained, but reworking is required and production efficiency decreases
Solution Approach 1:
The alignment mark is created in advance before dielectric layer deposition, ensuring it remains visible throughout the packaging process. This preliminary action eliminates the need for reworking to recreate alignment marks, allowing continuous production without interruptions and time losses associated with returning wafers to upstream providers.
4Difficulty of detecting and measuring
If a metal layer with thickness of not less than 0.3 μm is deposited as UBM layer, then the alignment mark becomes visible and recognizable, but the manufacturing process becomes more complex
Solution Approach 1:
The metal layer deposited as UBM (Under Bump Metallization) serves dual functions: it provides the necessary electrical connection and mechanical support for bump structures, and simultaneously creates a visible alignment mark on the wafer surface. This multi-functionality eliminates the need for separate alignment mark creation steps, reducing overall process complexity while ensuring mark visibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures continuous production by maintaining visibility of alignment marks, preventing reworking, and enhancing production efficiency by providing a clear and recognizable alignment mark, thus saving labor and material costs.
Implementation Method 1
removing the photoresist layer other than a target position... removing the photoresist other than the target position by means of a development technique. the development technique is to dissolve the photoresist in a region other than the target position by using a chemical developer
Implementation Method 2
covering an upper surface of the wafer with a metal layer having a thickness of not less than 0.3 μm, wherein the metal layer is a UBM layer shaped on the upper surface of the wafer
Data Source
AI summary
The present invention provides a method for preparing a dielectric layer on a surface of a wafer, a wafer structure, and a method for shaping a bump. The preparation method includes: providing a wafer; forming an alignment mark on the wafer, the thickness of the alignment mark being not less than 0.3 μm; and forming a dielectric layer on the wafer where the alignment mark is formed. In the present application, before the dielectric layer is shaped on a surface of the wafer, the alignment mark is prepared in advance on the surface of the wafer, thereby avoiding the need of reworking due to an invisible alignment mark in a preparation stage of the dielectric layer, and ensuring the continuity of the process.