Wafer Alignment Marks for Backside-Frontside Precision

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Solution Overview

Problem

Conventional methods for fabricating reverse conducting insulated-gate bipolar transistors (RC-IGBTs) face significant alignment errors between backside and frontside patterns on silicon wafers, typically exceeding 20 microns due to the inaccessible nature of the frontside during backside patterning, which is detrimental for precise device fabrication.

Innovation Solution

The method involves forming multiple sets of alignment marks on both sides of the semiconductor wafer, bonding a carrier wafer to improve handling, and using advanced alignment techniques like ASML 3DALIGN for precise three-dimensional alignment, followed by grinding, implanting, annealing, metallization, and singulation processes to achieve precise alignment and device formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional notch-based alignment method is used, then the backside patterning process is simple, but the alignment accuracy between backside pattern and frontside pattern deteriorates to 20 microns or worse

Engineering Contradiction:

Improvebackside patterning process simplicityVSAvoidalignment accuracy between backside and frontside patterns

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

Alignment marks are formed on the frontside of the wafer before backside patterning begins. These pre-formed marks serve as reference points that are visible and accessible during subsequent backside processing, enabling precise alignment without requiring complex real-time measurement systems during the actual patterning operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A carrier wafer is introduced as an intermediary substrate to hold the thinned device wafer during backside processing. The carrier wafer provides mechanical support and stability, allowing the fragile thinned wafer to be handled and processed with precise alignment while protecting it from damage during the patterning operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If the wafer is thinned for backside access, then the backside becomes accessible for patterning, but the wafer becomes fragile and difficult to handle

Engineering Contradiction:

Improvebackside accessibility for patterningVSAvoidwafer mechanical strength

Core Design Contradiction:

Ease of operationVSStrength

Solution Approach 1:

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The wafer thickness parameter is dynamically adjusted during the manufacturing process. The wafer is thinned to the minimum required thickness for backside access, then bonded to a carrier for strength during processing, and finally thinned again after backside patterning is complete. This dynamic parameter change optimizes both accessibility and mechanical strength at different process stages.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces misalignment to less than 120 nanometers using an i-line stepper and less than 60 nanometers using a DUV stepper, enabling the fabrication of semiconductor devices with complex structures requiring tight tolerances and precise metal pattern etching.

Implementation Method 1

forming a bonded wafer by bonding a carrier wafer to the semiconductor device wafer

Methodology Applied

Scientific EffectBonding: Welding

Implementation Method 2

The alignment accuracy is improved and can be as good as a solely frontside process only. For example, the misalignment is less than 120 nanometers by using an i-line stepper and the misalignment is less than 60 nanometers by using a DUV stepper.

Methodology Applied

Scientific EffectOptical alignment:

Implementation Method 3

applying a grinding process

Methodology Applied

Scientific EffectGrinding: Abrasion

Implementation Method 4

applying an implanting process

Methodology Applied

Scientific EffectIon implantation: Ion Implantation

Implementation Method 5

applying an implanting process and an annealing process

Methodology Applied

Scientific EffectAnnealing: Annealing

Data Source

PatentUS10833021B2Method for precisely aligning backside pattern to frontside pattern of a semiconductor wafer

Publication Date: 2020.11.10 ALPHA & OMEGA SEMICONDUCTOR (CAYMAN) LTD

AI summary

A method comprises the steps of providing a semiconductor device wafer; forming a first plurality of alignment marks on a first side of the semiconductor device wafer; forming a first pattern of a first conductivity type; forming a second plurality of alignment marks on a second side of the semiconductor device wafer; forming a bonded wafer by bonding a carrier wafer to the semiconductor device wafer; forming a third plurality of alignment marks on a free side of the carrier wafer; applying a grinding process; forming a plurality of device structure members; removing the carrier wafer; applying an implanting process and an annealing process; applying a metallization process and applying a singulation process.