Wafer Alignment Compensation for Topography-Driven Overlay Error

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing overlay errors during lithography patterning due to increased complexity and topographical variations in silicon wafers, which can distort alignment structures and lead to misalignment between successive layers, affecting device yield.

Innovation Solution

A lithographic overlay correction method that involves defining zones on the wafer and using either single-zone or multi-zone alignment compensation based on topographical variation, with multi-zone compensation using an equation to adjust alignment values across different zones, ensuring accurate wafer alignment and lithography exposure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If advanced lithography technologies are used to reduce geometry size, then production efficiency increases and costs decrease, but overlay errors increase and become more difficult to control

Engineering Contradiction:
Improveproduction efficiencyVSAvoidoverlay accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The wafer surface is divided into multiple zones (e.g., first zone, second zone, third zone) with different alignment compensation parameters. Each zone has its own set of alignment marks and compensation values, allowing independent optimization of alignment for different regions of the wafer, thereby reducing overall overlay errors while maintaining high productivity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different alignment compensation strategies are applied to different zones based on their specific topographical characteristics. The first zone uses a first set of compensation values, the second zone uses a second set, and the third zone uses a third set, allowing each region to be optimized for its local conditions rather than applying a uniform approach across the entire wafer

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If multi-zone alignment compensation is implemented to reduce overlay errors, then manufacturing precision improves, but device complexity increases

Engineering Contradiction:
Improvealignment accuracyVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The alignment compensation process is segmented into multiple zones, each with its own alignment marks and compensation parameters. This segmentation allows the complex problem of wafer-level alignment to be broken down into manageable zone-level problems, reducing the overall system complexity while improving precision

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes alignment parameters (compensation values) based on the zone being processed. By dynamically adjusting alignment parameters according to the specific zone and its topographical characteristics, the system achieves high precision without requiring a completely complex new approach,而是 by modifying existing parameters in a controlled manner

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11966170B2Lithographic overlay correction and lithographic process
Publication Date: 2024.04.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11966170B2 patent drawing
  • US11966170B2 patent drawing
  • US11966170B2 patent drawing

AI summary

A method includes receiving a wafer, measuring a surface topography of the wafer; calculating a topographical variation based on the surface topography measurement performing a single-zone alignment compensation when the topographical variation is less than a predetermined value or performing a multi-zone alignment compensation when the topographical variation is greater than the predetermined value; and performing a wafer alignment according to the single-zone alignment compensation or the multi-zone alignment compensation.