Wafer Alignment Compensation Using Regional Warpage Models

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Solution Overview

Problem

Existing photolithography processes face challenges in achieving accurate alignment of wafers with projection masks due to variations in wafer warpage and stress across different regions, leading to inconsistent alignment precision.

Innovation Solution

The method involves dividing the wafer into distinct regions based on warpage and stress patterns, determining separate alignment offset values and compensation equations for each region, and using these equations to adjust the alignment of the wafer and mask stage during exposure, ensuring precise alignment for each chip area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a single alignment model is used for the entire wafer, then the alignment process is simple and fast, but alignment precision varies significantly across different regions of the wafer

Engineering Contradiction:
Improvealignment precisionVSAvoidalignment model complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The wafer is divided into multiple regions (e.g., first region, second region, third region) based on warpage and stress characteristics. Each region has its own alignment model with region-specific alignment offset values and compensation equations, allowing precise alignment adaptation to local wafer conditions while maintaining manageable model complexity through modular organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different alignment compensation equations are applied to different regions of the wafer based on their specific warpage and stress patterns. The system determines whether a chip area is in a first region or second region and applies the corresponding alignment compensation equation, ensuring that each region receives optimized alignment treatment tailored to its local characteristics.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If the wafer is divided into multiple regions with separate alignment models, then alignment precision across all regions is improved, but the alignment process becomes more complex and time-consuming

Engineering Contradiction:
Improvemask pattern alignment accuracyVSAvoidalignment process time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Alignment offset values and compensation equations are pre-calculated and stored for each region before the actual exposure process. The system determines the region of the chip area and applies the corresponding pre-prepared alignment compensation equation, avoiding real-time complex calculations and reducing alignment process time while maintaining high precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The alignment system dynamically selects the appropriate alignment compensation equation based on the determined region of the chip area. This dynamic adaptation allows the system to efficiently switch between different alignment models without manual intervention, optimizing the balance between precision and processing time.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9348240B2Mask pattern alignment method and system
Publication Date: 2016.05.24 SEMICON MFG INT CORP
  • US9348240B2 patent drawing
  • US9348240B2 patent drawing
  • US9348240B2 patent drawing

AI summary

An alignment method includes dividing a wafer into a plurality of regions including a first region and a second region, and each region contains a plurality chip areas. The method also includes obtaining alignment offset values for the first region, and determining a first alignment compensation equation for the first region. The method also includes obtaining alignment offset values for the second region, and determining a second alignment compensation equation for the second region. Further, the method includes determining whether a chip area to be exposed is in the first region or the second region, when the chip area is in the first region, using the first alignment compensation equation to adjust alignment of the wafer and, when the chip area is in the second region, using the second alignment compensation equation to adjust the alignment of the wafer.