Wafer Alignment via Thermal Actuators
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Solution Overview
Problem
In semiconductor device fabrication, achieving high chip-to-chip accuracy during wafer-to-wafer bonding is hindered by incoming chip-to-chip misalignment, primarily due to global wafer-to-wafer runout and local distortion, which necessitates precise correction to minimize misalignment tolerance and silicon area usage.
Innovation Solution
A method and system that utilize thermal actuators arranged in an array to detect and correct planar distortions on wafer bonding surfaces by inducing thermal expansion or contraction based on detailed thermal modeling, creating non-uniform temperature and heat flux profiles to align and bond wafers accurately, incorporating Peltier and resistive elements for precise temperature control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional wafer-to-wafer bonding is used without thermal correction, then the process is simple and fast, but chip-to-chip alignment accuracy deteriorates due to global runout and local distortion
Solution Approach 1:
The system performs preliminary measurement of planar distortions on wafer bonding surfaces before bonding, and pre-calculates the thermal expansion corrections needed. The thermal actuators are pre-positioned and controlled to apply corrective thermal fields that compensate for measured distortions, ensuring alignment accuracy is achieved before the actual bonding occurs.
Solution Approach 2:
The system changes the temperature parameter locally across the wafer surface using an array of thermal actuators. By creating non-uniform temperature distributions, the system induces controlled thermal expansion or contraction in specific regions to correct planar distortions and achieve flat bonding surfaces with high alignment accuracy.
2Manufacturing precision
If thermal actuators are added to correct planar distortions, then alignment accuracy improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The thermal correction system is segmented into multiple independent thermal actuators arranged in an array beneath the wafer. Each actuator can be independently controlled to apply localized thermal corrections to specific regions of the wafer, allowing precise correction of complex distortion patterns while maintaining system modularity.
Solution Approach 2:
The system replaces mechanical correction methods (such as physical warping or mechanical pressing) with thermal fields. By using controlled thermal expansion and contraction, the system achieves planar distortion correction without complex mechanical actuators or contact-based mechanisms, simplifying the overall system architecture.
3Manufacturing precision
If non-uniform thermal fields are applied to correct local distortion, then chip-to-chip misalignment is reduced, but energy consumption and process time increase
Solution Approach 1:
The system applies thermal correction locally rather than uniformly across the entire wafer. By activating only the specific thermal actuators corresponding to regions with planar distortions, and by applying thermal fields only where needed, the system minimizes energy consumption while achieving effective correction of local distortions that affect alignment accuracy.
Solution Approach 2:
The system applies thermal correction partially, focusing only on the regions and magnitude necessary to achieve the required alignment tolerance. Rather than applying excessive thermal correction across the entire wafer, the system calculates and applies the minimum necessary thermal fields to correct measured distortions, optimizing energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves chip-to-chip alignment accuracy, reducing misalignment errors and substrate bow, enabling precise bonding with alignment accuracy in the range of 0 to 0.5 μm, particularly effective for challenging distortions that prior art solutions cannot correct.
Implementation Method 1
inducing thermal expansion or contraction based on detailed thermal modeling, creating non-uniform temperature and heat flux profiles to align and bond wafers accurately
Implementation Method 2
incorporating Peltier and resistive elements for precise temperature control
Implementation Method 3
incorporating Peltier and resistive elements for precise temperature control
Data Source
AI summary
A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding first and second circuitry-including wafers, each stage including a plurality of adjacent thermal actuators arranged in an array integrated with the stage; determining planar distortions of a bonding surface of the first and second circuitry-including wafers; mapping the planar distortions for each wafer based on the relative planar distortions thereon; deducing necessary local thermal expansion measurements for each wafer to compensate for the relative distortions based on the mapping; translating the thermal expansion measurements into a non-uniform wafer temperature profile model and a local heat flux profile model for each wafer; aligning the first and second wafers; and bonding the first and second wafers together. The bonding process includes simultaneously thermally treating at least one of the wafers in situ by individually adjusting the temperature of one or more thermal actuators in the array in accordance with the wafer temperature profile model and the local heat flux model to induce thermal expansion over a surface area corresponding to the dimensions of each adjusted thermal actuator.