Wafer Alignment Verification via Frame Segmentation and Scoring
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Solution Overview
Problem
Current semiconductor wafer inspection systems face challenges in accurately determining alignment, leading to potential defects being missed due to insufficient alignment quality, especially as dimensions shrink, and existing metrics lack granular information for troubleshooting wafer-to-wafer variations.
Innovation Solution
A system and method that includes a processor to position alignment verification locations on a wafer image, determining the distance to the closest alignment target and calculating an alignment score based on the number of frames between these locations, allowing for improved alignment assessment and defect detection, even without detected defects, and enabling alignment setup adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alignment verification locations are positioned per alignment frame to determine granular alignment scores, then alignment assessment accuracy is improved, but system complexity increases
Solution Approach 1:
The wafer image is divided into multiple alignment frames, and alignment verification locations are positioned within each frame. This segmentation allows granular alignment assessment at the frame level rather than treating the entire wafer as a single unit, thereby improving measurement precision while maintaining manageable system complexity through modular processing
Solution Approach 2:
The patent introduces a spatial dimension to alignment verification by positioning specific verification locations within alignment frames and calculating distances to alignment targets. This transforms alignment assessment from a global metric to a localized spatial measurement, enabling more precise alignment scoring based on the number of frames between verification locations and targets
2Difficulty of detecting and measuring
If existing alignment metrics are used without granular information, then troubleshooting capability is limited, but implementation simplicity is maintained
Solution Approach 1:
The system provides feedback through alignment scores that indicate the quality of alignment at specific verification locations. By calculating the number of frames between alignment verification locations and alignment targets, the system generates actionable feedback that helps identify areas with insufficient alignment, enabling targeted troubleshooting and adjustments
Solution Approach 2:
Alignment verification locations are positioned in advance within alignment frames before defect detection occurs. This preliminary positioning ensures that alignment quality is assessed proactively, allowing the system to identify and address alignment issues before they cause defect detection failures, thereby improving troubleshooting capability
3Area of stationary object
If alignment targets are spaced far apart to cover large wafer areas, then alignment coverage is improved, but alignment accuracy deteriorates
Solution Approach 1:
The wafer surface is segmented into multiple alignment frames with alignment verification locations positioned in each frame. This segmentation allows the system to maintain frequent verification points (improving alignment accuracy) while collectively covering the entire wafer area (maintaining alignment coverage). Each frame acts as an independent verification zone
Solution Approach 2:
The patent applies local quality by assessing alignment accuracy independently at each alignment verification location within alignment frames. Rather than using a single global alignment metric, the system evaluates alignment quality locally at each frame, allowing areas with different alignment characteristics to be assessed appropriately while maintaining overall wafer coverage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides more accurate alignment scores and defect detection, enabling timely troubleshooting and improving yield management by ensuring high alignment accuracy across the wafer, reducing the risk of missed defects and process variations.
Implementation Method 1
a light source that directs a light beam at a wafer, a stage configured to hold the wafer, a detector that receives the light beam reflected off the wafer
Data Source
AI summary
Alignment can be monitored by positioning at least one alignment verification location per alignment frame. The alignment verification location is a coordinate within the alignment frame. A distance between each of the alignment verification locations and a closest instance of an alignment target is determined. An alignment score can be determined based on the distance. The alignment score can include a number of the alignment frames between the alignment verification location and the alignment target. If the alignment score is below a threshold, then alignment setup can be performed.