Wafer Alignment via Via Center Averaging

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Solution Overview

Problem

Current wafer alignment methods, particularly in photolithography, face challenges due to changes in alignment marks during semiconductor processing, leading to misalignment issues that result in device failures and high yield loss, as traditional methods are either inaccurate or inefficient in accounting for variations in via size, shape, and location.

Innovation Solution

A semiconductor processing system determines the average center location of individual vias on a wafer and adjusts the wafer position relative to a processing tool based on this average, using digital imaging and algorithms for filtering, edge detection, and shape recognition to reduce alignment errors, regardless of variations in via size, shape, or topography.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If traditional alignment marks are used to align the wafer, then the alignment process is simplified, but the alignment precision deteriorates due to changes in mark features during processing

Engineering Contradiction:

Improvealignment process simplicityVSAvoidalignment precision

Core Design Contradiction:

Ease of operationVSManufacturing precision

Solution Approach 1:

The patent extracts the alignment function from traditional dedicated alignment marks and transfers it to vias that are inherently part of the device structure. By using vias as alignment features, the system eliminates the need for separate alignment marks that undergo processing-induced changes, thereby maintaining alignment precision while simplifying the overall process.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The via structures serve multiple functions: they provide electrical connectivity between layers and simultaneously serve as alignment marks for subsequent photolithography steps. This multi-functionality eliminates the need for dedicated alignment marks, resolving the contradiction between operational simplicity and alignment precision.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If dedicated alignment marks are used, then alignment reference is provided, but the marks undergo processing changes that cause misalignment

Engineering Contradiction:

Improvealignment reference stabilityVSAvoidmark feature stability

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The via structures are self-aligned through the manufacturing process itself. The vias are formed through standard semiconductor fabrication steps, and their positions are determined by the underlying layer geometry. This self-service approach ensures that the alignment features remain stable and consistent throughout processing, eliminating the misalignment problems associated with dedicated alignment marks.

Inventive Principle:

Principle #25Self-service

3Ease of operation

If manual alignment methods are used, then operator control is achieved, but alignment accuracy and productivity deteriorate

Engineering Contradiction:

Improveoperator controlVSAvoidalignment accuracy

Core Design Contradiction:

Ease of operationVSManufacturing precision

Solution Approach 1:

The patent replaces manual mechanical alignment operations with an automated optical measurement and calculation system. The system uses digital imaging to capture via positions, applies computational algorithms to determine center locations and offsets, and automatically calculates correction values. This substitution eliminates operator-dependent variability while maintaining ease of operation through automated control.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Adaptability or versatility

If via variations in size, shape, and location are accommodated, then alignment adaptability improves, but measurement and detection difficulty increases

Engineering Contradiction:

Improvealignment adaptability to via variationsVSAvoidvia center location detection difficulty

Core Design Contradiction:

Adaptability or versatilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent employs advanced image processing algorithms that can detect and measure via center locations despite variations in via size, shape, and topography. The system transforms the detection problem by using computational methods that are insensitive to these parameter variations, thereby maintaining high measurement accuracy while accommodating via variations.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The system captures digital images of the via pattern, calculates the actual center locations, determines offsets from expected positions, and uses this feedback information to compute wafer alignment corrections. This closed-loop feedback approach enables the system to adapt to via variations while maintaining precise alignment measurement.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10600667B2Systems and methods for wafer alignment

Publication Date: 2020.03.24 MICRON TECHNOLOGY INC

AI summary

Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.