Wafer Allocation for Semiconductor Deposition Alignment
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Solution Overview
Problem
In semiconductor device manufacturing, achieving high integration of non-volatile storage devices requires increasing the aspect ratio of hole patterns to enhance memory cell stacking efficiency, but existing technologies face challenges in accurately aligning and depositing stacked bodies across multiple stages, leading to misalignments and variations in feature amounts.
Innovation Solution
A deposition supporting system that includes a host computer, surface shape measurement apparatus, wafer conveyance apparatus, and depositing apparatus, which evaluates feature amounts and allocates wafers to stations based on specified criteria to minimize misalignments between first and second stacked bodies, using evaluation formulas to ensure feature amounts fall within permissible values, thereby improving alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the aspect ratio of hole patterns is increased to enhance memory cell stacking efficiency, then the integration density is improved, but the alignment accuracy between stacked bodies deteriorates
Solution Approach 1:
The system performs preliminary evaluation of feature amounts (such as position, shape, and dimensions of hole patterns) before the deposition process. Based on this evaluation, wafers are pre-sorted and allocated to specific deposition stations that can best accommodate their characteristics, thereby preparing for accurate alignment before the actual stacking operation begins
Solution Approach 2:
The patent applies different evaluation criteria and allocation strategies to different regions or types of wafers based on their specific feature amounts. Each wafer is assessed individually for its hole pattern characteristics, and deposition parameters are optimized locally for each wafer-station combination to maintain alignment accuracy despite varying aspect ratios
2Manufacturing precision
If wafers are allocated to different deposition stations, then the variation in feature amounts is reduced, but the complexity of the allocation system increases
Solution Approach 1:
The system implements a feedback mechanism where feature amounts of wafers are measured and evaluated, and this information is fed back to the allocation unit. The allocation unit uses this feedback to dynamically assign wafers to appropriate deposition stations, creating a closed-loop control system that reduces feature amount variation through intelligent routing
Solution Approach 2:
The patent changes the allocation parameters from simple sequential assignment to multi-dimensional criteria including wafer position, hole pattern dimensions, shape characteristics, and deposition station capabilities. This parameter transformation enables more precise matching between wafers and stations, reducing feature variation despite increased system complexity
3Productivity
If the number of deposition stations is increased to handle more wafers, then the batch processing capacity is improved, but the time for wafer allocation and management increases
Solution Approach 1:
The system performs wafer evaluation and station allocation in advance before the actual deposition sequence begins. By pre-determining the optimal station assignment for each wafer based on their feature amounts, the system avoids time-consuming decisions during the deposition process itself, thereby managing increased batch capacity efficiently
Solution Approach 2:
The patent divides the batch processing into segments where wafers with similar characteristics are grouped and assigned to specific deposition stations. This segmentation allows for optimized processing of each group simultaneously, increasing overall batch capacity while reducing the complexity of managing individual wafer allocations across all stations
Data Source
AI summary
According to one embodiment, deposition supporting system, depositing apparatus and manufacturing method of a semiconductor device includes a depositing apparatus that deposits stacked bodies on wafers allocated to stations and a host computer. The host computer evaluates feature amounts convertible to misalignments at predetermined points on the stacked bodies of the respective wafers, and specifies the stations to which the wafers are to be allocated based on the feature amounts of the stacked bodies in the respective stations. The depositing apparatus allocates the wafers to the stations based on the specification from the host computer.